Patents by Inventor Subhash Rewachand Nariani

Subhash Rewachand Nariani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Wafer-level chip scale package
    Patent number: 8710664
    Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: April 29, 2014
    Assignee: Volterra Semiconductor Corporation
    Inventors: Efren M. Lacap, Subhash Rewachand Nariani, Charles Nickel
  • Wafer-Level Chip Scale Package
    Publication number: 20130026638
    Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.
    Type: Application
    Filed: January 30, 2012
    Publication date: January 31, 2013
    Inventors: Efren M. Lacap, Subhash Rewachand Nariani, Charles Nickel
  • Wafer-level chip scale package
    Patent number: 8106516
    Abstract: A chip scale package implements solder bars to form a connection between a chip and a trace, formed in a substrate, such as another chip or PCB. Solder bars are formed by depositing one or more solder layers into the socket, or optionally, depositing a base metal layer into the socket and applying the solder layer to the base metal layer. The geometry of a solder bars may be rectangular, square, or other regular or irregular geometry. Solder bars provide a greater utilization of the connectivity footprint and increase the electrical and thermal flow capacity. Solder bars also provide a robust connection.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: January 31, 2012
    Assignee: Volterra Semiconductor Corporation
    Inventors: Efren M. Lacap, Subhash Rewachand Nariani, Charles Nickel