Abstract: A trace assist unit operable with a plurality of processor cores is described. The trace assist unit comprises a plurality of physical buffers, and loading circuitry and unloading circuitry that are communicatively coupled with the plurality of physical buffers. The loading circuitry receives trace events from various ones of the plurality of processor cores, each of the trace events having a respective category from a plurality of predefined categories. The loading circuitry writes the trace events to respective ones of the plurality of physical buffers that are assigned to the respective categories of the plurality of predefined categories. The loading circuitry transmits, responsive to one or more predefined conditions, an unload signal to the unloading circuitry to unload contents of a selected physical buffer of the plurality of physical buffers to an external memory.

Abstract: Adapter snooping in hardware using a split structure cache includes: receiving, by a hardware snooping module, a completion packet from a network adapter, storing, by the hardware snooping module, a data structure associated with the completion packet in a split structure cache included within the hardware snooping module, performing, by the hardware snooping module, a hardware snoop on the data structure, including updating the data structure based on the completion packet, where the hardware snooping module is configured to determine whether to interrupt firmware based on the hardware snoop of the data structure, and sending, by the hardware snooping module, the updated data structure to system memory.

Abstract: A trace assist unit operable with a plurality of processor cores is described. The trace assist unit comprises a plurality of physical buffers, and loading circuitry and unloading circuitry that are communicatively coupled with the plurality of physical buffers. The loading circuitry receives trace events from various ones of the plurality of processor cores, each of the trace events having a respective category from a plurality of predefined categories. The loading circuitry writes the trace events to respective ones of the plurality of physical buffers that are assigned to the respective categories of the plurality of predefined categories. The loading circuitry transmits, responsive to one or more predefined conditions, an unload signal to the unloading circuitry to unload contents of a selected physical buffer of the plurality of physical buffers to an external memory.