Abstract: Systems and methods of verifying a hardware processing circuit design for a digital system are disclosed. Three different computer models of the same hardware are implemented. The first computer model is implemented on a first sequence of action inputs and a second sequence of action inputs. The second computer model is implemented on the first sequence of action inputs and is allowed to idle until the first sequence is done. The architectural states of the second computer model are then recorded. The third computer model is implemented on the second sequence after having set the third computer model to the recorded architectural states. The outputs of the first computer model and the third computer model are implemented to check for functional consistency. The techniques described herein can be used to check digital designs for functional consistency, are sound and complete, and do not require an understanding of implementation details.

Abstract: The present description concerns a memory module (100) adapted to implementing computing operations, the module comprising a plurality of elementary blocks (110) arranged in an array according to rows and columns, wherein: each elementary block (110) comprises a memory circuit (111) adapted to implementing computing operations, and a configurable transfer circuit (113); each configurable transfer circuit (113) is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit (120) is connected to an input-output port (123) of the module; and the internal control circuit (120) is configured to read at least one instruction signal from the input-output port (123) of the module and accordingly parameterize the configuration of the configurable transfer circuits (113), and define the size of the operand vectors of the computing operations.

Abstract: The present description concerns a memory module (100) adapted to implementing computing operations, the module comprising a plurality of elementary blocks (110) arranged in an array according to rows and columns, wherein: each elementary block (110) comprises a memory circuit (111) adapted to implementing computing operations, and a configurable transfer circuit (113); each configurable transfer circuit (113) is parameterizable to transmit data originating from a first transmit elementary block to a receive elementary block of a same column of elementary blocks via at least one link bus; an internal control circuit (120) is connected to an input-output port (123) of the module; and the internal control circuit (120) is configured to read at least one instruction signal from the input-output port (123) of the module and accordingly parameterize the configuration of the configurable transfer circuits (113), and define the size of the operand vectors of the computing operations.

Abstract: The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Abstract: The present disclosure relates to a method of programming resistive memory cells of a resistive memory, the method comprising: applying, by a programming circuit based on a first target resistive state, an initial resistance modification to a first cell of the resistive memory to change its resistance from an initial resistive state to a first new resistance; comparing, by the programming circuit, the first new resistance of the first cell with a resistance range of the first target resistive state and with a target resistance range associated with the first target resistive state; and if it is determined that the first new resistance is outside the resistance range of the target resistive state and inside the target resistance range, applying by the programming circuit one or more further resistance modifications to the first cell to increase or decrease its resistance.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods—which we call Quick Error Detection—Hardware (QED-H)—advantageously quickly detect and fix anomalies (bugs) within SoC hardware components—and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead.

Abstract: An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. Our methods—which we call Quick Error Detection—Hardware (QED-H)—advantageously quickly detect and fix anomalies (bugs) within SoC hardware components—and in particular customized SoC hardware components that are not necessarily software programmable. Of further advantage, methods according to the present disclosure are compatible with existing Quick Error Detection (QED) techniques while being extensible to target software-programmable components as well. In sharp contrast to prior art methods, method(s) according to the present disclosure represent a new system validation methodology that builds validation checks in both software and hardware components seamlessly and systematically, thus enabling extremely quick error detection and localization for all digital components of the entire SoC advantageously producing productivity and time-to-market gains.

Abstract: Disclosed are improved methods and structures for verifying integrated circuits and in particular systems-on-a-chip constructed therefrom. We call methods and structures according to the present disclosure Symbolic Quick Error Detection or Symbolic QED, Illustrative characteristics of Symbolic QED include: 1) It is applicable to any System-on-Chip (SoC) design as long as it contains at least one programmable processor; 2) It is broadly applicable for logic bugs inside processor cores, accelerators, and uncore components; 3) It does not require failure reproduction; 4) It does not require human intervention during bug localization; 5) It does not require trace buffers, 6) It does not require assertions; and 7) It uses hardware structures called “change detectors” which introduce only a small area overhead.

Abstract: A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.

Abstract: An apparatus for detecting bugs in a logic-based processing device during post-silicon validation is disclosed. The apparatus includes a test bench and a Proactive Load and Check (PLC) hardware checker inserted within an uncore component of the logic-based processing device. The test bench includes a processor for converting an original test program to a modified test program for validating the functionalities of the logic-based processing device during post-silicon validation. The PLC hardware checker includes a controller, an address generator, a data register and a comparator.

Abstract: A method of operating a test device for a logic-based processing device includes the steps of providing an original set of test instructions, generating one or more Quick Error Detection (QED) test programs, and causing the one or more QED test programs to be executed on the logic-based processing device. Each one of the QED test programs includes the original test program with additional instructions inserted at strategic locations within the original set, wherein the additional instructions and the strategic locations vary between each of the QED test programs.

Abstract: A method for validating a nanotube logic network. The nanotube logic network is separated into regions based on a conductivity of the respective region. Potential paths through adjoining regions of the nanotube logic network are determined. Boolean path functions for each potential path are determined. If the Boolean path functions of the potential paths are equivalent to the intended logic function, then the nanotube logic network is immune to misaligned carbon nanotubes.

Abstract: A wafer-scale multiple carbon nanotube transfer process is provided. According to one embodiment of the invention, plasma exposure processes are performed at various stages of the fabrication process of a carbon nanotube device or article to improve feasibility and yield for successive transfers of nanotubes. In one such carbon nanotube transfer process, a carrier material is partially etched by a plasma process before removing the carrier material through, for example, a wet etch. By applying the subject plasma exposure processes, fabrication of ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics is facilitated. The ultra-high-density nanotubes and ultra-high-density nanotube grids or fabrics fabricated utilizing embodiments of the invention can be used, for example, to make high-performance carbon nanotube field effect transistors (CNFETs) and low cost, highly-transparent, and low-resistivity electrodes for solar cell and flat panel display applications.

Abstract: A logic cell that is immune to misaligned carbon nanotubes. Carbon nanotubes are positioned on a substrate. Contacts are formed on a layer of carbon nanotubes, including a first input contact, a second input contact, an output contact, a first gate region, and a second gate region. The output contact is positioned between the first input contact and the second input contact, and a cell region is provided bounded by a width of the output contact and residing between the first input contact and the second input contact. A nonconductive region is positioned in the layer of carbon nanotubes between any two or more of the plurality of contacts that, if shorted, would inhibit a logic function.

Abstract: Circuit responses to a stimulus may be compacted, decreasing the number of pin outs, without increasing the circuit element length, using a compactor. In accordance with one embodiment of the present invention, errors may be detected in scan chains used for integrated circuit testing. The number of outputs applied to output pins or other connectors may be substantially decreased, resulting in cost savings.

Abstract: A compactor has a reduced number of outputs and the ability to handle a higher number of errors and unknown logic values. The procedure for designing the matrix and the resulting compactor involves determining the number of unknown logic values that may be encountered and adding columns to the compactor matrix based on the number of errors. Basically, the number of possible combinations of scan in lines is determined. Then, additional columns are added for each possible combination of scan in lines. The number of columns that are added for each combination of scan in lines is equal to the number of errors plus one in one embodiment.

Abstract: In one embodiment, an apparatus is provide with a combinational logic circuit to generate a data input signal; a delay element, coupled to the combinational logic circuit, to provide a delayed data input signal in response to the data input signal. Additionally, the apparatus is provided with a system bistable circuit, coupled to the combinational logic circuit, to generate a system bistable signal in response to at least the data input signal; a shadow bistable circuit, coupled to the delay element, to generate a shadow bistable signal in response to at least the delayed data input signal. Further, the apparatus is provided with an output joining circuit, coupled to the system and the shadow bistable circuits, to provide a data output signal in response to the system and the shadow bistable signals.