Patents by Inventor Subhra MAZUMDAR

Subhra MAZUMDAR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12056506
    Abstract: In a Coarse-Grained Reconfigurable Architecture (CGRA) system, two configuration files are used. The CGRA system has an array of configurable units that includes a plurality of switches, a print configurable unit, a source configurable unit, and one or more sink configurable units, The first configuration file, upon being executed by the CGRA system, configures the CGRA system to send output data directly from the source configurable unit to the one or more sink configurable units through the plurality of switches. The second configuration file, upon being executed into the CGRA system, configures the CGRA system to send the output data from the source configurable unit to the print configurable unit through the plurality of switches, send the output data from the print configurable unit to both a memory that is accessible by a host computing unit, and the one or more sink configurable units.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: August 6, 2024
    Assignee: SambaNova Systems, Inc.
    Inventors: Joshua Brot, Raghu Prabhakar, Subhra Mazumdar, James Decker, Tram Tran
  • Publication number: 20240231903
    Abstract: In a computer-implemented method a Dynamic Transfer Engine (DTE) included in a computing system receives a dynamic stimulus associated with transfer of stage data during execution of a dataflow application by the system. The DTE determines, based on source and destination devices of the transfer, a transfer method and a transfer channel to transfer the stage data between memories coupled to the source and destination devices. The DTE acquires, hardware resources of the computing system to transfer the stage using the channel and, initiates the transfer. A computer program product can cause one or more processors to perform the method. A computing system can comprise source and destination processors and memories, hardware channels to transfer data between the memories, a resource manager, and a DTE configured to perform the method.
    Type: Application
    Filed: March 23, 2024
    Publication date: July 11, 2024
    Applicant: SambaNova Systems, Inc.
    Inventors: Qi ZHENG, Arnav GOEL, Conrad Alexander TURLIK, Guoyao FENG, Joshua Earle POLZIN, Fansheng CHENG, Ravinder KUMAR, Greg DYKEMA, Subhra MAZUMDAR, Milad SHARIF, Jiayu BAI, Neal SANGHVI, Arjun SABNIS, Letao CHEN
  • Publication number: 20230259823
    Abstract: In a method an orchestrator of a computing system determines that results of Machine Learning model computations are available and dispatches a worker to perform model computations that include computing gradients of the results. The orchestrator determines that a set of gradients of the results is available and dispatches a gradient worker to compute a sum of the gradients. The orchestrator determines that a second set of gradients of the results is available and dispatches a second gradient worker to compute a sum of the second set of gradients. The orchestrator determines that the sums of the first and second gradients are available and dispatches a third gradient worker to compute synchronized gradients. The gradient workers compute the sums and synchronized gradients concurrent with training workers computing additional model computations results and/or gradients. A computer program product can include the method and a computing system can include the orchestrator.
    Type: Application
    Filed: February 13, 2023
    Publication date: August 17, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Greg DYKEMA, Fansheng CHENG, Kuan ZHOU, Arnav GOEL, Subhra MAZUMDAR, Milad SHARIF, Po-Yu WU, Bowen YANG, Qi ZHENG
  • Publication number: 20230251989
    Abstract: A data processing system is presented that includes multiple local buses, a host processor, a network interface controller (NIC) for connecting to external storage via a network, one or more reconfigurable processors, and a bus switch. The bus switch couples the multiple local busses, thereby operatively coupling the one or more reconfigurable processors, the host processor, and the NIC. The one or more reconfigurable processors are configured to implement a virtual function that uses a virtual address for a memory access operation. The host processor is configured to implement an application programming interface (API) that translates the virtual address into a physical address, and the NIC uses the physical address to initiate a direct data access operation at the external storage that moves data directly between the one or more reconfigurable processors and the external storage, wherein the data bypasses the host processor.
    Type: Application
    Filed: February 9, 2023
    Publication date: August 10, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Subhra MAZUMDAR, Guoyao FENG, Neal SANGHVI
  • Publication number: 20230205580
    Abstract: A computer implemented method comprises a server processing work requests of a work requester. The work requester can communicate to the server a processing dependency of one work request on a second work request. The server can associate the dependency with the work requests and/or a queue of work requests. The dependency include a condition to be met in association with processing the work requests, and the condition can include an action for the server to take in association with processing a work request. A computing system can comprise a work requester, a server, and a set of dependency-aware queues for processing a set of work requests. A queue and/or work requests on the queues can be associated with a processing dependency and the server can process work requests enqueued to the queues in an order based on the dependencies. A work requester/server interface can comprise a dependency framework.
    Type: Application
    Filed: June 22, 2022
    Publication date: June 29, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Timmy Wu, Subhra Mazumdar
  • Publication number: 20230205499
    Abstract: A computer implemented method comprises a server processing work requests of a work requester. The work requester can communicate to the server a processing dependency of one work request on a second work request. The server can associate the dependency with the work requests and/or a queue of work requests. The dependency include a condition to be met in association with processing the work requests, and the condition can include an action for the server to take in association with processing a work request. A computing system can comprise a work requester, a server, and a set of dependency-aware queues for processing a set of work requests. A queue and/or work requests on the queues can be associated with a processing dependency and the server can process work requests enqueued to the queues in an order based on the dependencies. A work requester/server interface can comprise a dependency framework.
    Type: Application
    Filed: June 22, 2022
    Publication date: June 29, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Timmy Wu, Subhra Mazumdar
  • Publication number: 20230195478
    Abstract: In a Coarse-Grained Reconfigurable Architecture (CGRA) system, two configuration files are used. The CGRA system has an array of configurable units that includes a plurality of switches, a print configurable unit, a source configurable unit, and one or more sink configurable units, The first configuration file, upon being executed by the CGRA system, configures the CGRA system to send output data directly from the source configurable unit to the one or more sink configurable units through the plurality of switches. The second configuration file, upon being executed into the CGRA system, configures the CGRA system to send the output data from the source configurable unit to the print configurable unit through the plurality of switches, send the output data from the print configurable unit to both a memory that is accessible by a host computing unit, and the one or more sink configurable units.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 22, 2023
    Applicant: SambaNova Systems, Inc.
    Inventors: Joshua BROT, Raghu PRABHAKAR, Subhra MAZUMDAR, James DECKER, Tram TRAN
  • Patent number: 10761846
    Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: September 1, 2020
    Assignee: Oracle International Corporation
    Inventor: Subhra Mazumdar
  • Publication number: 20190171453
    Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.
    Type: Application
    Filed: January 18, 2019
    Publication date: June 6, 2019
    Inventor: Subhra Mazumdar
  • Patent number: 10296996
    Abstract: Systems and methods for planning location-sensitive probabilistic behavior based evacuation paths, in a building, from source nodes to sink nodes in a network of routes including a plurality of vertices and edges are disclosed. For example, input parameters including layouts, number of evacuees at each source node, transit time, predetermined time period and maximum capacity associated with each edge and vertex are received. Further, weak evacuation schedules at a state of the evacuees are defined based on the layouts of the building, number of evacuees, transit time and predetermined time period. Furthermore, a strong evacuation schedule is defined based on the weak evacuation schedules and maximum capacity associated with each edge and vertex. Moreover, a mapping is defined from the strong evacuation schedule to the weak evacuation schedules to obtain a probabilistic behavior model. Also, an evacuation path is planned, in real-time, based on the probabilistic behavior model.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 21, 2019
    Assignee: Tata Consultancy Services Limited
    Inventors: Arindam Pal, Francesco Parisi, Venkatramanan Siva Subrahmanian, Subhra Mazumdar
  • Patent number: 10185564
    Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: January 22, 2019
    Assignee: Oracle International Corporation
    Inventor: Subhra Mazumdar
  • Patent number: 9972176
    Abstract: Methods and systems for planning evacuation paths are provided to identify an optimum path for evacuation of every evacuee from a region of interest. Methods of the instant disclosure ensure that for each suggested evacuation path, the capacity of any edge on the path is not exceeded and the evacuation time is minimum. A path once identified is maintained. A randomized behavior model is employed to re-distribute evacuees in emergency situations. This provides optimum evacuation time that employs an improved technique with optimized run time and evacuation time after taking into consideration herd behavior.
    Type: Grant
    Filed: July 19, 2016
    Date of Patent: May 15, 2018
    Assignee: Tata Consultancy Services Limited
    Inventors: Arindam Pal, Gopinath Mishra, Subhra Mazumdar
  • Publication number: 20170315806
    Abstract: An apparatus includes a buffer, a sequencing circuit, and an execution unit. The buffer may be configured to store a plurality of instructions. Each of the plurality of instructions may be in a first thread. In response to determining that the first instruction depends on the value of a condition variable and to determining that a count value is below a predetermined threshold, the sequencing circuit may be configured to add a wait instruction before the first instruction. The execution unit may be configured to delay execution of the first instruction for an amount of time after executing the wait instruction. The sequencing circuit may be further configured to maintain the plurality of instructions in the first buffer after executing the wait instruction, and to decrement the count value in response to determining that the value of the condition variable is updated within the amount of time.
    Type: Application
    Filed: April 28, 2016
    Publication date: November 2, 2017
    Inventor: Subhra Mazumdar
  • Publication number: 20170243316
    Abstract: Systems and methods for planning location-sensitive probabilistic behavior based evacuation paths, in a building, from source nodes to sink nodes in a network of routes including a plurality of vertices and edges are disclosed. For example, input parameters including layouts, number of evacuees at each source node, transit time, predetermined time period and maximum capacity associated with each edge and vertex are received. Further, weak evacuation schedules at a state of the evacuees are defined based on the layouts of the building, number of evacuees, transit time and predetermined time period. Furthermore, a strong evacuation schedule is defined based on the weak evacuation schedules and maximum capacity associated with each edge and vertex. Moreover, a mapping is defined from the strong evacuation schedule to the weak evacuation schedules to obtain a probabilistic behavior model. Also, an evacuation path is planned, in real-time, based on the probabilistic behavior model.
    Type: Application
    Filed: July 19, 2016
    Publication date: August 24, 2017
    Applicant: Tata Consultancy Services Limited
    Inventors: Arindam PAL, Francesco PARISI, Venkatramanan Siva Subrahmanian, Subhra MAZUMDAR
  • Publication number: 20170053503
    Abstract: Methods and systems for planning evacuation paths are provided to identify an optimum path for evacuation of every evacuee from a region of interest. Methods of the instant disclosure ensure that for each suggested evacuation path, the capacity of any edge on the path is not exceeded and the evacuation time is minimum. A path once identified is maintained. A randomized behavior model is employed to re-distribute evacuees in emergency situations. This provides optimum evacuation time that employs an improved technique with optimized run time and evacuation time after taking into consideration herd behavior.
    Type: Application
    Filed: July 19, 2016
    Publication date: February 23, 2017
    Applicant: Tata Consultancy Services Limited
    Inventors: Arindam PAL, Gopinath MISHRA, Subhra MAZUMDAR