Patents by Inventor Subhrajit ROY

Subhrajit ROY has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210319009
    Abstract: Aspects described herein include a method of generating three-dimensional (3D) spikes. The method comprises receiving a signal comprising time-series data and generating a first two-dimensional (2D) grid. Generating the first 2D grid comprises mapping segments of the time-series data to respective positions of the first 2D grid, and generating, for each position, a spike train corresponding to the respective mapped segment. The method further comprises generating a second 2D grid including performing, for each position, a mathematical operation on the spike train of the corresponding position of the first 2D grid. The method further comprises generating a third 2D grid including performing spatial filtering on the positions of the second 2D grid. The method further comprises generating a 3D grid based on a combination of the first 2D grid, the second 2D grid, and the third 2D grid. The 3D grid comprises one or more 3D spikes.
    Type: Application
    Filed: April 8, 2020
    Publication date: October 14, 2021
    Inventors: Umar ASIF, Subhrajit ROY, Jianbin TANG, Stefan HARRER
  • Publication number: 20180356771
    Abstract: A computer system is proposed including an adaptive signal processing model of a kind in which a multiplicative section, such as a VLSI integrated circuit, processes data input to the model, using hidden neurons and randomly-set variables, and an adaptive output layer processes the outputs of the multiplicative section using variable parameters. Controllable switching circuitry is proposed to control which data inputs are fed to which hidden neurons, to reduce the number of hidden neurons required and increase the effective number of data inputs. An algorithm is proposed to selectively disable unnecessary hidden neurons. Normalisation, and a winner-take all stage, may be provided at the hidden layer output.
    Type: Application
    Filed: September 16, 2016
    Publication date: December 13, 2018
    Inventors: Arindam BASU, Yi CHEN, Subhrajit ROY, Enyi YAO, Aakash Shantaram PATIL