Abstract: A data driving circuit including: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line.

Abstract: A light emitting display apparatus includes a display portion including a plurality of pixel driving lines disposed over a substrate and a plurality of pixels selectively connected to the plurality of pixel driving lines, a light emitting device layer disposed at the display portion, a dam portion including at least one dam having a metal line, a plurality of switching circuit portions disposed to overlap the at least one dam and selectively connected to the plurality of pixel driving lines, and a front pad portion including a plurality of front pads electrically coupled to the plurality of pixel driving lines and the metal line of the at least one dam, each of the plurality of switching circuit portions includes first and second switching circuits each including a gate electrode electrically coupled to the metal line of the at least one dam.

Abstract: A display apparatus includes a display panel, a data analyzer, a logic core and a latch. The display panel is configured to display an image. The data analyzer is configured to analyze input image data. The logic core is configured to compensate all of line data, compensate a part of the line data, or not compensate all of the line data according to an analysis result of the data analyzer. The latch is configured to receive compensated data from the logic core.

Abstract: Disclosed is a display device. The display device of the present disclosure includes: a display panel; a rear frame which is positioned in a rearward direction of the display panel; an inner frame which is positioned between the display panel and the rear frame, and coupled to the rear frame; and an outer frame which is coupled to the inner frame, and supports a rear surface of the display panel.

Abstract: A data driver includes output channels configured to output data signals, output controllers selectively outputting data signals having a first arrangement or data signals having a second arrangement to output channel groups each of which includes N output channels in response to arrangement control signals, where N is a positive integer greater than or equal to 2, and a control signal generator outputting the arrangement control signals to the output controllers to control the output controllers.

Abstract: Disclosed is a display device, which includes a display panel, a controller that receives an image signal and an external synchronization signal and generates a control signal, and a driver that generates a driving signal in response the control signal and provides the driving signal to the display panel. The controller includes a synchronization signal generator that generates an internal synchronization signal based on a reference clock signal, a corrector that corrects the internal synchronization signal to generate a corrected synchronization signal, and a control signal generator that generates the control signal, and the control signal generator generates the control signal based on the external synchronization signal when the external synchronization signal is in a normal state, and generates the control signal based on the internal synchronization signal when the external synchronization signal is in an abnormal state.

Abstract: The present disclosure relates to a display apparatus and a multi-screen display apparatus including the same. The display apparatus includes a substrate including a display area including a plurality of pixels disposed along a first direction and a second direction intersecting with the first direction, and a gate driving circuit including a plurality of stage circuit units respectively disposed at a plurality of horizontal lines of the display area to supply a scan signal to the plurality of pixels. Each of the plurality of stage circuit units includes a plurality of branch circuits supplying the scan signal to the plurality of pixels, and a plurality of circuit connection lines connected to the plurality of branch circuits and formed of a transparent conductive material.

Abstract: A data driving circuit including: a latch which receives an output image signal and outputs a latch data signal including a plurality of bits; a transition detector which compares the latch data signal of a current line with the latch data signal of a previous line, and outputs a first transition detection signal based on the comparison; a delay compensator which outputs a delay data signal obtained by delaying some of the plurality of bits of the latch data signal based on the first transition detection signal; a level shifter which outputs a level shift data signal obtained by changing a voltage level of the delay data signal; and an output circuit which converts the level shift data signal into a data signal and provides the data signal obtained by converting the level shift data signal to a data line.

Abstract: An electronic device includes: a near field communication (NFC) circuit; at least one processor operatively connected to the NFC circuit; and memory storing instructions that, when executed by the at least one processor, cause the electronic device to: receive, via the NFC circuit from an external electronic device, an NFC application identifier (ID), identify a subscriber identity module (SIM) profile, from among a plurality of SIM profiles, that corresponds to the NFC application ID, and perform, via the NFC circuit, an NFC communication with the external electronic device based on the identified SIM profile.

Abstract: An electronic device is provided. The electronic device includes a camera, a memory, and at least one processor electrically coupled to the camera and the memory. The at least one processor may obtain a plurality of image frames through the camera, in response to a shooting start command, obtain a shooting command subsequent to the shooting start command, select a first number of image frames from among the plurality of image frames obtained before the shooting command, in response to the shooting command, and generate a first image synthesized based on the selected first number of image frames.

Abstract: A display apparatus can include a display panel in which pixels, first to gth gate lines, and data lines are provided (where g is a natural number), and link lines provided on a rear surface of the display panel and connected to the data lines provided on a front surface of the display panel. In a display area including the pixels in the front surface, a first stage to an mth stage generating gate signals to be supplied to the first gate line to the gth gate line are provided (where m is a natural number less than or equal to g). A first monitoring line through which a first monitoring signal is output is further connected to the first stage, and the first monitoring line extends to the rear surface through a lateral surface of the display panel.

Abstract: Disclosed is a display device, which includes a display panel, a controller that receives an image signal and an external synchronization signal and generates a control signal, and a driver that generates a driving signal in response the control signal and provides the driving signal to the display panel. The controller includes a synchronization signal generator that generates an internal synchronization signal based on a reference clock signal, a corrector that corrects the internal synchronization signal to generate a corrected synchronization signal, and a control signal generator that generates the control signal, and the control signal generator generates the control signal based on the external synchronization signal when the external synchronization signal is in a normal state, and generates the control signal based on the internal synchronization signal when the external synchronization signal is in an abnormal state.

Abstract: A display apparatus includes a display panel, a data analyzer, a logic core and a latch. The display panel is configured to display an image. The data analyzer is configured to analyze input image data. The logic core is configured to compensate all of line data, compensate a part of the line data, or not compensate all of the line data according to an analysis result of the data analyzer. The latch is configured to receive compensated data from the logic core.

Abstract: A display apparatus includes a substrate including a display area including a plurality of pixels disposed along a first direction and a second direction intersecting with the first direction, a gate driving circuit disposed at each of a plurality of horizontal lines of the display area, the gate driving circuit including a plurality of stage circuit units for supplying a scan signal to the plurality of pixels, a plurality of gate control lines connected to the plurality of stage circuit units disposed at the display area, a plurality of dummy lines disposed respectively adjacent to the plurality of gate control lines, and a plurality of carry signal lines connected between the plurality of stage circuit units disposed at the display area, each of the plurality of carry signal lines may comprise a plurality of line patterns disposed at different layers.

Abstract: A display apparatus includes a display panel in which pixels, signal lines connected to the pixels, and gate lines supplying gate signals to the pixels are provided, and link lines provided on a rear surface of the display panel and connected to the signal lines provided on a front surface of the display panel, wherein a test unit is provided at ends of the link lines on the rear surface.

Abstract: A gamma voltage control circuit includes a first amplifier and a second amplifier. The first amplifier is configured to generate a first primitive reference voltage based on a panel power voltage applied to a display panel. The second amplifier is configured to generate a first reference voltage based on the first primitive reference voltage, the panel power voltage and an internal power voltage.

Abstract: A semiconductor package includes an interposer, an electronic device having a first side surface and a second side surface opposite to the first side surface, and including a plurality of memory dies stacked in a vertical direction, at least one first through pipe passing through the electronic device in the vertical direction adjacent to the first side surface, and moving a cooling liquid therein, and a plurality of thermal transmission lines extending in a horizontal direction inside the memory die, and extending in parallel from the first through pipe toward the second side surface.

Abstract: Disclosed is a display device. The display device of the present disclosure includes: a display panel; a rear frame which is positioned in a rearward direction of the display panel; an inner frame which is positioned between the display panel and the rear frame, and coupled to the rear frame; and an outer frame which is coupled to the inner frame, and supports a rear surface of the display panel.

Abstract: A display apparatus includes a display panel in which pixels, signal lines connected to the pixels, and gate lines supplying gate signals to the pixels are provided, and link lines provided on a rear surface of the display panel and connected to the signal lines provided on a front surface of the display panel, wherein a test unit is provided at ends of the link lines on the rear surface.

Abstract: A display device is disclosed. The display device includes: a display panel; an optical layer configured to be a diffusion plate positioned behind the display panel; a reflecting sheet configured to be positioned at the rear side of the optical layer behind the diffusion plate; a frame configured to be positioned behind the reflecting sheet; and a supporter configured to be positioned between the optical layer diffusion plate and the reflecting sheet so that the optical layer diffusion plate and the reflecting sheet are spaced apart from each other and to have an elastic portion that at least partially deforms upon deformation of the optical layer diffusion plate. According to the present invention, even if the optical layer diffusion plate deforms, the possibility of damage to the optical layer diffusion plate due to the supporter with the elastic portion can be reduced.