Abstract: A system and method for optimizing memory bus bandwidth, is achieved by utilization of the memory bus, either by utilizing the idle time of the memory bus, or by prioritizing prefetch requests to exploit the bank structure of the external memory. When a bus master of the memory bus makes a request to access a particular line in a memory device, the memory controller generates a request for accessing a line next to the current line that is requested by the bus master. Data corresponding to the next line is retrieved from the memory device and stored in the memory-controller when the memory bus is idle. The stored data may be served to a bus master upon request for the data. However, the memory bus is not engaged when the data stored in the memory controller is served. Therefore idle time of the memory bus is utilized.

Abstract: A computer system includes a microprocessor, a cache memory, main memory and supporting logic. The supporting logic includes cache control logic that determines whether an access to memory results in a hit to the cache for dirty or clean data. When a write to the cache results in a hit to clean data, the bus cycle is enlarged in order to set a dirty bit associated with the write data. The bus cycle is enlarged by requesting the processor to refrain from commencing a new bus cycle or driving a new memory address.

Abstract: A memory access chip set includes a data buffer chip and a system controller chip. The data buffer chip contains storage elements that buffer data values transferred between a memory and either the host data bus or the peripheral bus. In one aspect, the storage elements are transparent latches, and not master/slave flip-flops. In another aspect, the storage elements are operated asynchronously. In another aspect, the storage elements are exactly two levels deep (additional accommodations are made in the case of data busses having mismatched widths). The arrangement of storage elements is such that only a single control pin is required on the data buffer chip to enable them, and only a single input pin (plus, in some cases, a clock input pin) for externally coordinating outputs from the storage elements for synchronous transfer over the destination bus.

Abstract: Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

Abstract: Method and apparatus for reducing the access time required to write to memory and read from memory in a computer system having a cache-based memory. A dynamic determination is made on a cycle by cycle basis of whether data should be written to the cache with a dirty bit asserted, or the data should be written to both the cache and main memory. The write-through method is chosen where the write-through method is approximately as fast as the write-back method. Where the write-back method is substantially faster than the write-through method, the write-back method is chosen.

Abstract: In a computer system, one or more ISA connector sockets is replaced by a connector structure which carries both ISA signals and local bus signals. The connector structure is arranged such that a standard ISA accessory card may be inserted, in which case only ISA signals are coupled to or from the card. "Local bus" accessory cards may also be designed for insertion into such a connector, and these cards may connect to one or more signal lines of the local bus either additionally or instead of connections made to the ISA bus. By physical or other means, ISA accessory cards are prevented from unintentional contact with connector contacts which are coupled to local bus signal lines. The connector structure may advantageously comprise an EISA-type connector socket.