Abstract: Methods and apparatuses for determining in-plane distortion (IPD) across a substrate having a plurality of patterned regions. A method includes obtaining intra-region data indicative of a local stress distribution across one of the plurality of patterned regions; determining, based on the intra-region data, inter-region data indicative of a global stress distribution across the substrate; and determining, based on the inter-region data, the IPD across the substrate.

Abstract: Methods and apparatuses for determining in-plane distortion (IPD) across a substrate having a plurality of patterned regions. A method includes obtaining intra-region data indicative of a local stress distribution across one of the plurality of patterned regions; determining, based on the intra-region data, inter-region data indicative of a global stress distribution across the substrate; and determining, based on the inter-region data, the IPD across the substrate.

Abstract: Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.

Abstract: Certain aspects of the present disclosure provide techniques for increasing processor caching efficiency by cache data pattern optimization. One embodiment includes a method for managing data in a cache, including: receiving data to be cached at the cache; determining that the data to be cached matches a predefined data pattern; and updating a tag RAM associated with the cache with a pattern tag comprising tag bits and pattern bits, wherein the pattern bits match the predefined data pattern.

Abstract: Aspects of the present disclosure provide a method of operating a system-on-chip (SoC). The method includes determining efficiency of a memory of the SoC over a defined period of time, calculating an adjusted bandwidth for operating the memory based on the determined efficiency, and adjusting at least one of a voltage or a clock of the memory corresponding to the adjusted bandwidth.

Abstract: Systems and methods are disclosed for improved processor hang detection. An exemplary method comprises setting a timer with a hang threshold value for each of a plurality of processors of a system on a chip (SoC). The hang threshold value represents a time in microseconds. The method further comprising receiving a first heartbeat signal from each of the plurality of processors with detection logic hardware of a hang controller coupled to the plurality of processors and to the timer. The timer is reset for each of the plurality of processors if a second heartbeat signal is received from the corresponding one of the plurality of processors before the timer expires. Alternatively, a hang event notification is generated if the second heartbeat signal is not received from the corresponding one of the plurality of processors before the timer expires.

Abstract: Dynamic predictive wake-up techniques are disclosed. A central processing unit (CPU) may initiate an input/output (I/O) transfer. The CPU may ascertain if a predicted time for the transfer exceeds an amount of time required to enter and exit a low-power mode and enter the low-power mode after the transfer is initiated. An I/O controller may calculate how long the transfer will take and compare that calculation to a known exit latency associated with the CPU. The calculated value is decremented by the amount of the known exit latency and the I/O controller may generate an early wake command at the decremented value. The CPU receives the early wake command and wakes such that the CPU is awake and ready to process data at conclusion of the transfer.

Abstract: Disclosed is a method for protecting virtual machine data at a peripheral subsystem connected to at least one processor configured to host a plurality of virtual machines. In the method, context information, including a virtual machine identifier (VMID), is received. The VMID is unique to one of the plurality of virtual machines. A storage bank of a plurality of storage banks is selected based on the VMID included in the received context information. Each storage bank of the plurality of storage banks uses a same bus address range. A data bus is connected to the selected storage bank.

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract: A portable computing device is arranged with one or more subsystems that include a processor and a memory management unit arranged to execute threads under a subsystem level operating system. The processor is in communication with a primary memory. A first area of the primary memory is used for storing time critical code and data. A second area is available for demand pages required by a thread executing in the processor. A secondary memory is accessible to a hypervisor. The processor generates an interrupt when a page fault is detected. The hypervisor, in response to the interrupt, initiates a direct memory transfer of information in the secondary memory to the second area available for demand pages in the primary memory. Upon completion of the transfer, the hypervisor communicates a task complete acknowledgement to the processor.

Abstract: A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.

Abstract: One or more triggers may be coupled to sources on a system on a chip of a portable computing device. The sources monitor the system for status conditions. The one or more triggers are coupled to a trigger bus. A sequencer engine is coupled to the trigger bus and a communication bus. The sequencer engine receives one or more instructions from the communication bus for determining how the sequencer engine should monitor the one or more triggers via the trigger bus and preserve data received from the one or more triggers before a system reset. The sequencer engine then receives data from the one or more triggers and stores the data in local memory storage. The sequencer engine, if programmed, may generate at least one of a trace packet, an interrupt signal, and a general purpose input/output signal in response to receiving data from one or more triggers.

Abstract: A processor reset control circuit is configured to automatically capture a pre-reset value of processor information stored in one or more hardware registers, as part of a reset operation state machine and prior to changing the processor information to its architecturally required post reset value. Such pre-reset processor information includes, for example one or more pre-reset values of the processor program counter (PC) and one or more pre-reset values of an operating-state mode register, both of which may be captured in one or more pre-reset capture storage devices which are then made available for evaluation purposes. Such pre-reset capture storage devices store pre-reset information in response to the reset and maintain the stored pre-reset information until another reset occurs.