Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A system for controlling an RF gain of a receiver that reduces a time taken to maintain an input signal level at an optimum dynamic range is provided. The system includes a tuner that receives a radio frequency (RF) signal and down-converts the RF signal to an intermediate frequency (IF) signal, and a demodulator. The tuner includes a radio frequency programmable gain amplifier (RF_VGA), a filter and an IF programmable gain amplifier (IF_VGA). The demodulator includes an analog to digital converter (ADC), and an Automatic Gain Control (AGC) unit that (i) receives a digital signal and an IF gain of the IF_VGA. The ADC samples a filtered IF signal under oversampling conditions to obtain an oversampled signal that includes an in-band signal and an out-of-band signal. The AGC unit (ii) controls the RF_VGA, the IF_VGA and (iii) measures an RF energy of the RF signal.

Abstract: A receiver system for early detection of a segment type of an input signal based on BPSK and DBPSK modulated carriers is provided. The receiver system includes a tuner that converts the input signal into an intermediate frequency (IF) signal, a signal conditioning module that converts the IF signal into a baseband signal, a Frequency Domain Synchronization (FDS) block that detects the segment type of the input signal based on a carrier powers, a Transmission and Multiplexing Configuration Control (TMCC) decode block that performs a decoding operation on the received signal, a channel estimation block that estimates a channel and obtains a channel information. The TMCC decode block uses the channel information obtained from channel estimation block to correct a fast-frequency selective fading on the received signal before the decoding operation.

Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Abstract: A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mth harmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mth harmonic to obtain a peak position (PPOS), and a carrier frequency offset estimation unit that receives the peak position (PPOS) and estimates the CFO.

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract: A method for implementing a digital filter is provided. The method includes (a) determining a bit-width of an incoming data sample of an incoming signal by measuring a distance between a leading zero or one of the incoming data sample and a trailing zero of the incoming data sample. The incoming data sample is obtained by sampling the incoming signal at a pre-defined time interval, (b) obtaining bit-width multipliers with variable bit-widths based on a first probability distribution function (PDF) of bit-widths of incoming data samples, (c) allocating the incoming data sample and a filter coefficient based on the bit-width of the incoming data sample and a bit-width of the filter coefficient to one bit-width multiplier of the bit-width multipliers, and (d) performing a multiply operation of a Multiply and Accumulate (MAC) operation on the one bit-width multiplier to generate an output of the digital filter.

Abstract: A wide band receiver to select and demodulate an input signal with single scan spectrum sensing by performing filtering on the input signal in digital domain to achieve improved selectivity and sensitivity is provided. The input signal includes one or more narrowband radio frequency (RF) signals. The wide band receiver includes a wide band tuner that down converts the one or more narrowband RF signals to one or more IF signals. An analog to digital converter (ADC) converts the one or more IF signals to one or more digital signals. A filter rejects out-of-band signals from the one or more digital signals to achieve the improved selectivity. A numeric controlled oscillator (NCO) selects at least one narrowband digital signal from the digital signals based on a phase value obtained from a spectrum selection control unit. A demodulator demodulates the narrowband digital signal to obtain a demodulated digital signal.

Abstract: A receiver for reducing acquisition time of a Carrier Frequency Offset (CFO) of an input intermediate frequency (IF) signal with M-PSK modulated preamble using spectral based analysis is provided. The receiver includes an analog to digital converter that converts the input IF signal into a digital signal, a down conversion unit that down converts the digital signal to a baseband complex signal, and a CFO estimation block that estimates the CFO. The CFO estimation block includes a carrier harmonic generation unit that generates an output of carrier Mth harmonic without modulation in the baseband complex signal, a spectral mapping unit that spectrally maps the carrier harmonic using complex Fast Fourier Transform, a spectral analysis unit that performs peak search on the spectrally mapped carrier Mth harmonic to obtain a peak position (PPOS), and a carrier frequency offset estimation unit that receives the peak position (PPOS) and estimates the CFO.

Abstract: A system and method for reducing implementation complexity for estimation of a Carrier Frequency Offset (CFO) and a Symbol Timing Offset (STO) for an input signal for spectrally shaped multiple communication standards. The system is implemented by replacing multiplier with shifters. The system includes a CFO estimation block, a STO estimation block, and a band extraction block that extracts a lower band edge and an upper band edge of the input signal. The STO estimation block includes (i) a sample error generation block that computes a sampling timing error value, and (ii) a Phase Lock Loop block that estimates a frequency error and a phase error corresponding to the sampling timing error value. The CFO estimation block includes (i) a carrier offset error generation block that generates a carrier offset error value, and (ii) a leaky average block for performing a filter operation.

Abstract: A system for controlling an RF gain of a receiver that reduces a time taken to maintain an input signal level at an optimum dynamic range is provided. The system includes a tuner that receives a radio frequency (RF) signal and down-converts the RF signal to an intermediate frequency (IF) signal, and a demodulator. The tuner includes a radio frequency programmable gain amplifier (RF_VGA), a filter and an IF programmable gain amplifier (IF_VGA). The demodulator includes an analog to digital converter (ADC), and an Automatic Gain Control (AGC) unit that (i) receives a digital signal and an IF gain of the IF_VGA. The ADC samples a filtered IF signal under oversampling conditions to obtain an oversampled signal that includes an in-band signal and an out-of-band signal. The AGC unit (ii) controls the RF_VGA, the IF_VGA and (iii) measures an RF energy of the RF signal.

Abstract: A receiver system for early detection of a segment type of an input signal based on BPSK and DBPSK modulated carriers is provided. The receiver system includes a tuner that converts the input signal into an intermediate frequency (IF) signal, a signal conditioning module that converts the IF signal into a baseband signal, a Frequency Domain Synchronisation (FDS) block that detects the segment type of the input signal based on a carrier powers, a Transmission and Multiplexing Configuration Control (TMCC) decode block that performs a decoding operation on the received signal, a channel estimation block that estimates a channel and obtains a channel information. The TMCC decode block uses the channel information obtained from channel estimation block to correct a fast-frequency selective fading on the received signal before the decoding operation.