Patents by Inventor Subrahmanyam Chivukula

Subrahmanyam Chivukula has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7776574
    Abstract: The invention relates to a thrombolytic enzyme referred to as Thrombinase having a molecular weight of 31,000 to 32,000. Such a thrombolytic enzyme can be used for dissolving blood clots. The process comprises culturing a filtrate of Bacillus sphaericus sero type H5a 5b, removing the cell, subjecting the cell supernatant to filtration, salting out the retentate, subjecting the precipitate to dialysis, reprecipitating the precipitate and then reconstituting in buffer and finally decolourizing, purifying and dialyzing.
    Type: Grant
    Filed: May 20, 2004
    Date of Patent: August 17, 2010
    Assignees: National Research Development Corporation, Malladi Drugs & Pharmaceuticals Ltd.
    Inventors: Perurmadom Ramaiyer Mahadevan, Sita Mahadevan, legal representative, Subrahmanyam Chivukula Sekar, Sundaramurthy Suresh Babu
  • Patent number: 6451704
    Abstract: A new method is provided for the creation of PLDD regions that is aimed at reducing lateral p-type impurity diffusion. The process starts with a silicon substrate on the surface of which gate electrodes have been created. An NLDD implantation is performed self-aligned with the NMOS gate electrode, a layer of oxide (oxide liner) is deposited over the structure over which a layer of nitride is deposited over which a first layer of top oxide is deposited. First gate spacers are formed by etching the first layer of top oxide, stopping on the nitride layer. NS/D and PS/D implantations are performed self-aligned with respectively the NMOS and the PMOS devices, the S/D implantations are annealed. The first gate oxide spacers are removed, a PLDD implantation is performed self-aligned with the PMOS gate electrode. A second layer of top oxide is deposited over the structure and etched to form the second gate spacers on the sidewalls of the NMOS and PMOS gate electrodes.
    Type: Grant
    Filed: May 7, 2001
    Date of Patent: September 17, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Yelehanka Ramachandramurthy Pradeep, Subrahmanyam Chivukula, Jie Ye, Madhudsudan Mukhopdhyay