Abstract: The memory building blocks can be used in conjunction with ASIC automatic design tools to generate a memory macro (e.g., a memory array) using a known ASIC design flow including, for example, register transfer level (RTL), synthesis, automatic place and route (APR) and timing analysis.

Abstract: A circuit having a first circuit configured to receive an input voltage and generate a first voltage that generates a first current flowing through a resistive device and a second voltage that generates a second current; a node electrically coupled to the resistive device and having a third voltage that generates a third current; and a second circuit configured to generate a fourth voltage having a logic state indicating a logic state of the resistive device.

Abstract: Some embodiments are related to a mesh capacitor, which improves the SER FIT rate. In an embodiment, the capacitor is connected between an input and an output of a latch in a flip-flop, making the flip-flop harder to flip due to radiation (e.g., from neutrons and/or alpha particles). In some embodiments, the capacitor is built directly vertically on top of the flip-flop, saving chip layout areas.

Abstract: An interleaved memory circuit includes a first memory bank having a first memory cell. A first local control circuit is coupled with the first memory bank. A second memory bank includes a second memory cell. A second local control circuit is coupled with the second memory bank. An IO block is coupled with the first memory bank and the second memory bank. A global control circuit is coupled with the first and second local control circuits. An interleaving access includes a clock signal having a first cycle and a second cycle for accessing the first memory cell and the second memory cell, respectively, wherein the second cycle is capable of enabling the first local control circuit to trigger a first transition of a first read column select signal RSSL for accessing the first memory cell.

Abstract: A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.

Abstract: A memory circuit includes a memory array, which further includes a plurality of memory cells arranged in rows and columns; a plurality of first bit-lines, each connected to a column of the memory array; and a plurality of write-assist latches, each connected to one of the plurality of first bit-lines. Each of the plurality of write-assist latches is configured to increase a voltage on a connecting one of the plurality of first bit-lines.

Abstract: An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.

Abstract: A memory circuit includes a bit line; a word line; a first power supply node having a first power supply voltage; a first power supply line connected to the first power supply node; a second power supply node selected from a group consisting of a floating node and a node having a second power supply voltage lower than the first power supply voltage; a second power supply line configured to switch connections between the first and the second power supply nodes; a write-assist-keeper (WAK) device coupling the first and the second power supply lines; and a static random access memory (SRAM) cell connected to the bit line, the word line and the second power supply line.

Abstract: A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.

Abstract: An SRAM device include: a latch unit for retaining data; one or more pass gate transistors controlled by a word line for coupling the latch unit to a bit line and a complementary bit line; and a power saving module coupled to the latch unit for raising a source voltage of the latch unit in response to a control signal on the word line, thereby reducing a leakage current for the latch unit.

Abstract: A method and system for testing the individual memory cells of a volatile memory cell array (e.g., SRAM) for data retention faults are described. In one embodiment of the invention, adjacent memory cells connected by a pair of common bit-lines are written with opposite, or complementary, data, for example, logical “0” and logical “1”. Next, the two memory cells are subjected to a stress condition by pre-charging the common bit-lines connecting the two adjacent memory cells, and then simultaneously asserting the word-line of each memory cell. Finally, the data in each cell is read and compared with the data written to the cell prior to generating the stress condition.

Abstract: A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

Abstract: Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.

Abstract: Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the memory bank segments are proximally positioned relative to associated I/Os. In this way, the delay times from each of the memory bank segments to their respective I/Os are substantially equal to each other. In addition, the proximal positioning of the memory banks results in reduced signal delays due to reduced signal paths from each bank segment and respective I/O.

Abstract: A 2T dual-port dynamic random access memory (DRAM) that can be fabricated using a pure logic process. Write/Refresh port is independent for any DRAM cell of the DRAM. Sense amplifier is built into each DRAM cell.

Abstract: Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the virtual memory banks has coupled to it an associated segmented sense amp which responds to an appropriate bank select signal by sensing data stored in a selected memory bank segment. The segmented sense amp uses a segmented bit line to reduce bit sense latency without decreasing bit density or increasing chip size.

Abstract: A static random access memory cell utilizes four NMOS transistors and does not require load elements. The semiconductor memory cell device maintains a stable data hold by utilizing a sub-threshold voltage to charge the word line, the sub-threshold voltage being higher than the low voltage reference of the memory cell device and lower than the threshold voltage of the NMOS access transistors. The sub-threshold voltage is biased to the word line during non-active and non-charging operations of the memory cell. The loadless four-transistor NMOS SRAM memory cell of the present invention requires a significantly smaller silicon area than prior art loadless four-transistor CMOS SRAM memory cells.

Abstract: A load-less 12-T TCAM wherein a TCAM cell uses two 1-bit 4-T SRAM storage cells that are scalable with technology. The TCAM has a TCAM cell that comprises two 1-bit 4-T SRAM data storage cells and a comparator. Within the TCAM cell, each of the two 1-bit 4-T SRAM storage cells is coupled to a BL by a pass-gate PMOS transistor that has a NP drain diode section. This NP drain diode section has a reverse-biased leakage current that is adapted to keep a dynamic node of the SRAM storage cell high without relying on any resistive-load element. The comparator is coupled to these two 1-bit 4-T SRAM storage cells. The comparator is adapted for matching a reference data with data communicated to the comparator from the two SRAM storage cells. The comparator is a 4-T comparator coupled to these two 4-T SRAM storage cells, thereby making the TCAM a 12-T load-less static TCAM.

Abstract: A content addressable memory (CAM) with built-in power saving management. The CAM includes a comparator circuit region that is coupled to a match line (ML) as well as a swing line (SL). The comparator circuit region is coupled to CAM cells. The comparator region is adapted for comparing match data with stored data within the CAM cells. The ML has its ML voltage level pre-charged to a pre-charge voltage level (Vc). Additionally, the SL is pre-charged to ground. In turn, in response to a data mismatch detected by the comparator, the ML voltage level drops from Vc by a ML voltage swing (Vswing) while the SL charge shares with the Ml. Advantageously, in response to this data mismatch, the SL charge shares with the ML such that Vswing is approximately less or equal to Vc/2. That is, the charge sharing prevents the ML from discharging all the way to ground.

Abstract: A ternary state content addressable memory (CAM) cell that includes two DRAM cells. In addition to a port for controlling and transmitting data to the CAM, another port is exclusively used for refreshing the DRAM cells. A refresh word line is coupled to the two DRAM cells for performing DRAW cell refresh. A refresh bit line is coupled to the first of the two DRAM cells for refreshing this first DRAM cell. A refresh bit line is coupled to the second of the two DRAM cells for refreshing this second DRAM cell. Problematic power consumption and voltage swing found in a conventional CAM are overcome in the CAM. A swing line (SL) is coupled to said first and second DRAM cells and a local match line (LML) of said CAM cell, said SL having an adjustable voltage level for changing voltage swing in said LML to regulate trade-off between power consumption and speed of said CAM cell.