Patents by Inventor Subramanian K.

Subramanian K. has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140357561
    Abstract: This document provides natriuretic polypeptide delivery systems. For example, methods and materials related to natriuretic polypeptide delivery systems, methods and materials related to the use of such delivery systems to deliver natriuretic polypeptides to a mammal over a pro-longed period of time (e.g., weeks to months), and methods and materials related to treating heart failure conditions are provided.
    Type: Application
    Filed: July 24, 2014
    Publication date: December 4, 2014
    Inventors: Horng H. Chen, John C. Burnett, JR., Lim Soo Ghim, Subramanian K. Venkatraman
  • Patent number: 8732974
    Abstract: A mobile device accessory for measuring a dimension is described. The accessory includes a housing having a mating feature that is adapted to mate with a corresponding mating feature of a mobile device. A measuring tape includes a detectable pattern thereon. The detectable pattern is related to the dimension. The accessory also includes a detector that generates a signal in response to detecting the pattern. A processor generates dimension data in response to receiving the signal. An interface transmits the dimension data to the mobile device.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: May 27, 2014
    Assignee: Symbol Technologies, Inc.
    Inventors: Ruwan Jayanetti, Subramanian K (Ks), Viputa Liyanaarachchi
  • Publication number: 20130305551
    Abstract: A mobile device accessory for measuring a dimension is described. The accessory includes a housing having a mating feature that is adapted to mate with a corresponding mating feature of a mobile device. A measuring tape includes a detectable pattern thereon. The detectable pattern is related to the dimension. The accessory also includes a detector that generates a signal in response to detecting the pattern. A processor generates dimension data in response to receiving the signal. An interface transmits the dimension data to the mobile device.
    Type: Application
    Filed: May 16, 2012
    Publication date: November 21, 2013
    Applicant: SYMBOL TECHNOLOGIES, INC.
    Inventors: Ruwan Jayanetti, Subramanian K (Ks), Vipula Liyanaarachchi
  • Patent number: 8549471
    Abstract: The present invention provides an open application program interface (API) service. A method of providing the API service includes generating meta-data for executing an API, generating resource data for generating a mash-up of the API, generating description data corresponding to the API, the meta-data, and the resource data, and generating an API package comprising the API, the meta-data, the resource data, and the description data. Accordingly, mash-up contents can be easily generated from various types of APIs.
    Type: Grant
    Filed: September 12, 2008
    Date of Patent: October 1, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-shin Jung, Joo-yeol Lee, Joe Antony Lawrence, Raghavendra Malapati, Subramanian K., Vinoth Sasidharan
  • Patent number: 8181132
    Abstract: In one embodiment, a method includes simulating by one or more computer systems a larger circuit to assign one or more values to one or more latch variables associated with the larger circuit, generating by the one or more computer systems one or more reduced circuits from the larger circuit according to the values assigned to the latch variables, generating by the one or more computer systems a transition relation (TR) for each reduced circuit, and generating by the one or more computer systems an initial state set for one or more instances of validation on the reduced circuits according to the TRs.
    Type: Grant
    Filed: April 30, 2009
    Date of Patent: May 15, 2012
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Mukul R. Prasad, Thomas W. Sidle
  • Patent number: 7788556
    Abstract: A method for evaluating an erroneous state associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are executed using the information in order to identify an erroneous state associated with a sub-space within the target circuit. A path associated with the erroneous state is identified. The path reflects a correlation between an initial state associated with the erroneous state and a point where the erroneous state was encountered.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: August 31, 2010
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo
  • Patent number: 7756953
    Abstract: A method is disclosed for monitoring responses of configuration commands using MIB-based and event-based approaches. According to one embodiment, a network element receives a configuration that comprises one or more configuration commands. A command response table, which comprises a plurality of command response entries, is created and stored. The command response table is defined by a MIB. The network element stores information, which describes errors that occurred while executing the plurality of commands in the configuration file, into the command response entries of the command response table. Management applications can query the MIB to obtain details about errors that occurred during execution of the configuration.
    Type: Grant
    Filed: April 2, 2008
    Date of Patent: July 13, 2010
    Assignee: Cisco Technology, Inc.
    Inventors: Rajesh Pulpatta, Subramanian K. Ramachandran
  • Publication number: 20090210212
    Abstract: In one embodiment, a method includes simulating by one or more computer systems a larger circuit to assign one or more values to one or more latch variables associated with the larger circuit, generating by the one or more computer systems one or more reduced circuits from the larger circuit according to the values assigned to the latch variables, generating by the one or more computer systems a transition relation (TR) for each reduced circuit, and generating by the one or more computer systems an initial state set for one or more instances of validation on the reduced circuits according to the TRs.
    Type: Application
    Filed: April 30, 2009
    Publication date: August 20, 2009
    Applicant: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Mukul R. Prasad, Thomas W. Sidle
  • Patent number: 7571403
    Abstract: In one embodiment, a method for verifying one or more particular properties of a circuit using a learning strategy to determine suitable values of particular verification parameters includes classifying each of multiple properties of a circuit according to circuit size and selecting a candidate property from the properties. The candidate property set includes one or more particular properties from each property class. The method also includes attempting to verify one or more particular properties of the circuit using the candidate property set and particular values of particular verification parameters. The method also includes determining suitable values of the particular verification parameters according the attempted verification of the particular properties of the circuit using the candidate property set and the particular values of the particular verification parameters.
    Type: Grant
    Filed: April 10, 2006
    Date of Patent: August 4, 2009
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier
  • Publication number: 20090158238
    Abstract: The present invention provides an open application program interface (API) service. A method of providing the API service includes generating meta-data for executing an API, generating resource data for generating a mash-up of the API, generating description data corresponding to the API, the meta-data, and the resource data, and generating an API package comprising the API, the meta-data, the resource data, and the description data. Accordingly, mash-up contents can be easily generated from various types of APIs.
    Type: Application
    Filed: September 12, 2008
    Publication date: June 18, 2009
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Dong-shin JUNG, Joo-yeol LEE, Joe Antony LAWRENCE, Raghavendra MALAPATI, Subramanian K., Vinoth SASIDHARAN
  • Patent number: 7546563
    Abstract: In one embodiment, a method for validating one or more circuits using one or more grids includes accessing a circuit and generating one or more seeds for executing one or more instances of validation on the circuit. Each instance of validation comprising one or more tasks. The method also includes distributing the tasks and the seeds across a grid including multiple nodes and, using the seeds, executing the instances of validation at the nodes in the grid according to the tasks.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: June 9, 2009
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Mukul R. Prasad, Thomas W. Sidle
  • Patent number: 7493376
    Abstract: A method is disclosed for monitoring responses of configuration commands using MIB-based and event-based approaches. According to one embodiment, a network element receives a configuration that comprises one or more configuration commands. A command response table, which comprises a plurality of command response entries, is created and stored. The command response table is defined by a MIB. The network element stores information, which describes errors that occurred while executing the plurality of commands in the configuration file, into the command response entries of the command response table. Management applications can query the MIB to obtain details about errors that occurred during execution of the configuration.
    Type: Grant
    Filed: December 24, 2002
    Date of Patent: February 17, 2009
    Assignee: Cisco Technology, Inc.
    Inventors: Rajesh Pulpatta, Subramanian K. Ramachandran
  • Publication number: 20080189446
    Abstract: A method is disclosed for monitoring responses of configuration commands using MIB-based and event-based approaches. According to one embodiment, a network element receives a configuration that comprises one or more configuration commands. A command response table, which comprises a plurality of command response entries, is created and stored. The command response table is defined by a MIB. The network element stores information, which describes errors that occurred while executing the plurality of commands in the configuration file, into the command response entries of the command response table. Management applications can query the MIB to obtain details about errors that occurred during execution of the configuration.
    Type: Application
    Filed: April 2, 2008
    Publication date: August 7, 2008
    Inventors: RAJESH PULPATTA, Subramanian K. Ramachandran
  • Publication number: 20080072190
    Abstract: In one embodiment, a method for validating one or more circuits using one or more grids includes accessing a circuit and generating one or more seeds for executing one or more instances of validation on the circuit. Each instance of validation comprising one or more tasks. The method also includes distributing the tasks and the seeds across a grid including multiple nodes and, using the seeds, executing the instances of validation at the nodes in the grid according to the tasks.
    Type: Application
    Filed: June 28, 2005
    Publication date: March 20, 2008
    Inventors: Jawahar Jain, Subramanian K. Iyer, Mukul R. Prasad, Thomas W. Sidle
  • Patent number: 7216312
    Abstract: In one embodiment, a method for determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures includes, at a first one of multiple computing systems, receiving a first partition of a circuit. The first partition corresponds to a first binary decision diagram (BDD) having a first density. The method includes performing a first reachability analysis on the first partition using the first BDD until a fixed point in the first partition has been reached and, if, during the first reachability analysis, the size of the first BDD exceeds a threshold, discarding the first BDD. The method includes communicating with at least one second one of the multiple computing systems. The second one of the multiple computing systems has received a second partition of the circuit. The second one of the multiple computing systems has performed a second reachability analysis on the second BDD without discarding the second BDD.
    Type: Grant
    Filed: November 7, 2003
    Date of Patent: May 8, 2007
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Amit Narayan, Yoshihisa Kojima, Takaya Ogawa, Subramanian K. Iyer, Debashis Sahoo
  • Patent number: 7032197
    Abstract: A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more operations may be executed in order to generate a set of transition relations for performing a reachability analysis associated with the target circuit. An image associated with the target circuit may be partitioned into a plurality of leaves that may each represent a subset of a final image to be generated by a partitioned ordered binary decision diagram (POBDD) data structure. An analysis may be computed of one or more of the leaves using a selected one or both of conjunction and quantification operations separately.
    Type: Grant
    Filed: June 4, 2003
    Date of Patent: April 18, 2006
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier
  • Patent number: 7028279
    Abstract: In one embodiment, a system for verifying a circuit using a scheduling technique includes one or more partitioned ordered binary decision diagram (POBDD) modules that collectively generate one or more POBDDs. Each POBDD corresponds to one or more partitions of a state space of the circuit and includes a number of states and a number of nodes in the partition. The system also includes one or more cost metrics modules that collectively determine a processing cost of each of the partitions of each of the POBDDs. The system also includes one or more scheduling modules that collectively schedule processing of the partitions of the POBDDs for semiformal verification of a circuit. The schedule is based, at least in part, on the determined processing costs of the partitions of the POBDDs.
    Type: Grant
    Filed: May 23, 2003
    Date of Patent: April 11, 2006
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier
  • Patent number: 6904578
    Abstract: A method for verifying a property associated with a target circuit is provided that includes receiving information associated with a target circuit, the information identifying a property within the target circuit to be verified. One or more partitioned ordered binary decision diagram (POBDD) operations are then executed using the information in order to generate a first set of states at a first depth associated with a sub-space within the target circuit. Bounded model checking may be executed using the first set of states in order to generate a second set of states at a second depth associated with the sub-space within the target circuit. The first set of states may be used as a basis for the second set of states such that the second depth is greater than the first depth.
    Type: Grant
    Filed: March 17, 2003
    Date of Patent: June 7, 2005
    Assignee: Fujitsu Limited
    Inventors: Jawahar Jain, Amit Narayan, Subramanian K. Iyer, Debashis Sahoo
  • Publication number: 20040199887
    Abstract: In one embodiment, a method for determining one or more reachable states in a circuit using distributed computing and one or more partitioned data structures includes, at a first one of multiple computing systems, receiving a first partition of a circuit. The first partition corresponds to a first binary decision diagram (BDD) having a first density. The method includes performing a first reachability analysis on the first partition using the first BDD until a fixed point in the first partition has been reached and, if, during the first reachability analysis, the size of the first BDD exceeds a threshold, discarding the first BDD. The method includes communicating with at least one second one of the multiple computing systems. The second one of the multiple computing systems has received a second partition of the circuit. The second one of the multiple computing systems has performed a second reachability analysis on the second BDD without discarding the second BDD.
    Type: Application
    Filed: November 7, 2003
    Publication date: October 7, 2004
    Inventors: Jawahar Jain, Amit Narayan, Yoshihisa Kojima, Takaya Ogawa, Subramanian K. Iyer, Debashis Sahoo
  • Publication number: 20040093571
    Abstract: In one embodiment, a system for verifying a circuit using a scheduling technique includes one or more partitioned ordered binary decision diagram (POBDD) modules that collectively generate one or more POBDDs. Each POBDD corresponds to one or more partitions of a state space of the circuit and includes a number of states and a number of nodes in the partition. The system also includes one or more cost metrics modules that collectively determine a processing cost of each of the partitions of each of the POBDDs. The system also includes one or more scheduling modules that collectively schedule processing of the partitions of the POBDDs for semiformal verification of a circuit. The schedule is based, at least in part, on the determined processing costs of the partitions of the POBDDs.
    Type: Application
    Filed: May 23, 2003
    Publication date: May 13, 2004
    Inventors: Jawahar Jain, Subramanian K. Iyer, Amit Narayan, Debashis Sahoo, Christian Stangier