Patents by Inventor Subramanian Karthikeyan
Subramanian Karthikeyan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7804291Abstract: A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.Type: GrantFiled: February 12, 2007Date of Patent: September 28, 2010Assignee: Agere Systems Inc.Inventors: Seung H. Kang, Lisa E. Mullin, Subramanian Karthikeyan, Sailesh M. Merchant
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Patent number: 7388395Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.Type: GrantFiled: April 13, 2006Date of Patent: June 17, 2008Assignee: Agere Systems Inc.Inventors: Seung H. Kang, Subramanian Karthikeyan, Sailesh M. Merchant
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Patent number: 7301107Abstract: An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.Type: GrantFiled: October 27, 2003Date of Patent: November 27, 2007Assignee: Agere Systems, Inc.Inventors: Subramanian Karthikeyan, Sailesh Mansinh Merchant
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Publication number: 20070168818Abstract: A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.Type: ApplicationFiled: February 12, 2007Publication date: July 19, 2007Applicant: Agere Systems, Inc.Inventors: Seung Kang, Subramanian Karthikeyan, Sailesh Merchant, Lisa Mullin
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Publication number: 20060192584Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.Type: ApplicationFiled: April 13, 2006Publication date: August 31, 2006Inventors: Seung Kang, Subramanian Karthikeyan, Sailesh Merchant
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Patent number: 7067419Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.Type: GrantFiled: November 25, 2003Date of Patent: June 27, 2006Assignee: Agere Systems, Inc.Inventors: Robert Y S Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt George Steiner, Joseph Ashley Taylor
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Patent number: 7061264Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151–156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121–126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.Type: GrantFiled: September 29, 2004Date of Patent: June 13, 2006Assignee: Agere Systems, Inc.Inventors: Seung H. Kang, Subramanian Karthikeyan, Sailesh M. Merchant
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Publication number: 20060066337Abstract: Method and test structures for determining heating effects in a test semiconductor device (10) are provided. The test device may include a first conductive metal structure (151-156) for accepting a flow of electric current that causes a heating effect. The test device may further include a second conductive metal structure proximate (121-126) the first conductive structure for obtaining resistivity changes in response to the heating effect. The resistivity changes are indicative of temperature changes due to the heating effect.Type: ApplicationFiled: September 29, 2004Publication date: March 30, 2006Inventors: Seung Kang, Subramanian Karthikeyan, Sailesh Merchant
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Publication number: 20060066335Abstract: A semiconductor test device includes a test circuit having contacts for applying an electrical signal and measuring electrical parameters of the test circuit. The semiconductor test device also includes an integrally formed heating circuit comprising at least one circuit meander positioned adjacent the test circuit for raising a temperature within a portion of the test circuit.Type: ApplicationFiled: September 28, 2004Publication date: March 30, 2006Inventors: Seung Kang, Subramanian Karthikeyan, Sailesh Merchant, Lisa Mullin
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Patent number: 7005375Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.Type: GrantFiled: September 30, 2002Date of Patent: February 28, 2006Assignee: Agere Systems Inc.Inventors: Subramanian Karthikeyan, Sailesh M. Merchant
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Publication number: 20040121579Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.Type: ApplicationFiled: November 25, 2003Publication date: June 24, 2004Inventors: Robert YS Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor
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Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device
Publication number: 20040084761Abstract: An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.Type: ApplicationFiled: October 27, 2003Publication date: May 6, 2004Inventors: Subramanian Karthikeyan, Sailesh Mansinh Merchant -
Publication number: 20040063307Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Subramanian Karthikeyan, Sailesh M. Merchant
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Method and structure of a reducing intra-level and inter-level capacitance of a semiconductor device
Publication number: 20030213617Abstract: An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.Type: ApplicationFiled: May 20, 2002Publication date: November 20, 2003Inventors: Subramanian Karthikeyan, Sailesh Mansinh Merchant -
Publication number: 20030119305Abstract: A mask layer having four mask films used in the fabrication of an interconnect structure of a semiconductor device. The first mask film and the third mask film have substantially equal etch rates. The second mask film and the fourth have substantially equal etch rates film, and different from that of the etch rate of the first and third mask films. A via is etched to the first mask film. Then a trench is etched to the third mask film of the mask layer. The via and trench are then etched in a dielectric material. The second, third and fourth mask films are removed and the first mask film remains a passivation layer for the dielectric material. A conductive metal is deposited in the via and trench.Type: ApplicationFiled: December 21, 2001Publication date: June 26, 2003Inventors: Robert Y. S. Huang, Scott Jessen, Subramanian Karthikeyan, Joshua Jia Li, Isaiah O. Oladeji, Kurt Geroge Steiner, Joseph Ashley Taylor
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Patent number: 6309900Abstract: Test structures are disclosed for use in a system and with an associated method to test the effectiveness of planarization systems used in the fabrication of semiconductor devices and integrated circuits. A method of creating the test structure utilizes traditional semiconductor fabrication techniques, but uses substantially similar materials, such as oxide, for each of the layers of the test structure. Because the test structure comprises layers of substantially the same material, reliable uniform measurements of the thickness of the test structure may be obtained by an optical metrology tool. These measurements may then be analyzed and displayed in tabular reports or multi-dimensional plots to judge the effectiveness of the planarization system.Type: GrantFiled: January 11, 2000Date of Patent: October 30, 2001Assignee: Agere Systems Guardian Corp.Inventors: Alvaro Maury, Frank Miceli, Subramanian Karthikeyan