Abstract: Embodiments of present disclosure relates to and systems to reduce propagation delays in hardware implementation of 3GPP confidentiality or standardized algorithm 128-EEA3 and 3GPP integrity algorithm 128-EIA3 using ZUC module. The reduction of the propagation delays is achieved by improving or optimizing secondary critical paths, which are subsequent to primary critical path, related to the 3GPP confidentiality or standardized algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. Non-conventional modifications in the hardware implementation are proposed for the improvement or optimization.

Abstract: Embodiments of present disclosure relates to and systems to reduce propagation delays in hardware implementation of 3GPP confidentiality or standardized algorithm 128-EEA3 and 3GPP integrity algorithm 128-EIA3 using ZUC module. The reduction of the propagation delays is achieved by improving or optimizing secondary critical paths, which are subsequent to primary critical path, related to the 3GPP confidentiality or standardized algorithm 128-EEA3 and the 3GPP integrity algorithm 128-EIA3. Non-conventional modifications in the hardware implementation are proposed for the improvement or optimization.

Abstract: Embodiments herein provide a method of parallel encoding of weight refinement in an adaptive scalable texture compression (ASTC) encoder. The method includes determining whether a neighbor weight index for a weight index is available in a decimated weight grid. Further, the method includes refining the neighbor weight index and the weight index in parallel, in response to determining that the neighbor weight index is available for the weight index.

Abstract: Embodiments herein provide a method of parallel encoding of weight refinement in an adaptive scalable texture compression (ASTC) encoder. The method includes determining whether a neighbor weight index for a weight index is available in a decimated weight grid. Further, the method includes refining the neighbor weight index and the weight index in parallel, in response to determining that the neighbor weight index is available for the weight index.

Abstract: A method of extracting error for peak signal to noise ratio (PSNR) computation in an adaptive scalable texture compression (ASTC) encoder. The method includes identifying a pixel positions of a pixel in a coded block. The pixel position corresponds to an index in a decimated weight block. The method extracts an error value corresponding to the identified pixel position for said PSNR computation in said ASTC encoder.

Abstract: A method of extracting error for peak signal to noise ratio (PSNR) computation in an adaptive scalable texture compression (ASTC) encoder. The method includes identifying a pixel positions of a pixel in a coded block. The pixel position corresponds to an index in a decimated weight block. The method extracts an error value corresponding to the identified pixel position for said PSNR computation in said ASTC encoder.

Abstract: A cache controller having a cache store and associated with a storage system maintains information stored in the cache store across a reboot of the cache controller. The cache controller communicates with a host computer system and a data storage system. The cache controller partitions the cache memory to include a metadata portion and log portion. A separate portion is used for cached data elements. The cache controller maintains a copy of the metadata in a separate memory accessible to the host computer system. Data is written to the cache store when the metadata log reaches its capacity. Upon a reboot, metadata is copied back to the host computer system and the metadata log is traversed to copy additional changes in the cache that have not been saved to the data storage system.

Abstract: A system and signal processing method, in which at least two processors have prioritized, shared access to one or more devices connected along a bus. In preferred embodiments, a fast processor is connected along a first bus, a slow processor and shared device are connected along a second bus, and a communication device is connected between the buses. The communication device is configured to provide the fast processor continuous access to the shared device (in response to grant of an access request by the fast processor) for a limited time that is longer than the time required for a single word transfer, but the slow processor must contend with the fast processor for access to the shared device each time after the slow processor completes a word transfer. Preferably, the communication device provides the fast processor continuous access to the shared device for up to a maximum number of word transfers in response to grant of one access request by the fast processor.

Abstract: A circuit and a method are provided for reducing power consumption in a phase-locked loop (PLL) by controlling how long the bias current for the charge pump is turned on. In such a circuit, a bias check circuit that indicates when the bias current has stabilized, and a self-adjusting control circuit including an internal counter are provided to measure how long the bias current takes to start up when the PLL is locked. Then the self-adjusting control circuit prevents the bias current from turning on until there is just enough time for it to stabilize before a charge pump event. A default control circuit is also provided to turn the bias current on for specified intervals when the PLL is out of lock.