Patents by Inventor Subramanian Tamilmani
Subramanian Tamilmani has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220389568Abstract: Methods for filling a substrate feature with a seamless metal gate fill are described. Methods comprise sequentially depositing a film on a substrate surface having at least one feature thereon. The at least one feature extends a feature depth from the substrate surface to a bottom surface and has a width defined by a first sidewall and a second sidewall. The film is treated with an oxidizing plasma. Then the film is etched to remove the oxidized film. A second film is deposited to fill the feature, where the second film substantially free of seams and voids.Type: ApplicationFiled: June 8, 2022Publication date: December 8, 2022Applicant: Applied Materials, Inc.Inventors: Subramanian Tamilmani, Srinivas Gandikota, Jianqiu Guo, Luping Li
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Patent number: 11133205Abstract: Apparatus and methods to process one or more substrate are described. A processing chamber comprises a support assembly, a chamber lid, and a controller. The chamber lid has a front surface facing the support assembly, a first sensor on the front surface and a second sensor on the front surface, the first sensor positioned at a first distance from the central rotational axis, and the second sensor positioned at a second distance from the central rotational axis greater than the first distance. The controller is configured to determine if a substrate is within or outside of the substrate support region of the support assembly.Type: GrantFiled: May 18, 2020Date of Patent: September 28, 2021Assignee: Applied Materials, Inc.Inventors: Sanggyum Kim, Prasanth Narayanan, Subramanian Tamilmani, Mandyam Sriram
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Publication number: 20200373178Abstract: Apparatus and methods to process one or more substrate are described. A processing chamber comprises a support assembly, a chamber lid, and a controller. The chamber lid has a front surface facing the support assembly, a first sensor on the front surface and a second sensor on the front surface, the first sensor positioned at a first distance from the central rotational axis, and the second sensor positioned at a second distance from the central rotational axis greater than the first distance. The controller is configured to determine if a substrate is within or outside of the substrate support region of the support assembly.Type: ApplicationFiled: May 18, 2020Publication date: November 26, 2020Applicant: Applied Materials, Inc.Inventors: Sanggyum Kim, Prasanth Narayanan, Subramanian Tamilmani, Mandyam Sriram
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Patent number: 10829864Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: GrantFiled: December 21, 2017Date of Patent: November 10, 2020Assignee: TruTag Technologies, Inc.Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
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Patent number: 10544519Abstract: During a pre-treat process, hydrogen plasma is used to remove contaminants (e.g., oxygen, carbon) from a surface of a wafer. The hydrogen plasma may be injected into the plasma chamber via an elongated injector nozzle. Using such elongated injector nozzle, a flow of hydrogen plasma with a significant radial velocity flows over the wafer surface, and transports volatile compounds and other contaminant away from the wafer surface to an exhaust manifold. A protective liner made from crystalline silicon or polysilicon may be disposed on an inner surface of the plasma chamber to prevent contaminants from being released from the surface of the plasma chamber. To further decrease the sources of contaminants, an exhaust restrictor made from silicon may be employed to prevent hydrogen plasma from flowing into the exhaust manifold and prevent volatile compounds and other contaminants from flowing from the exhaust manifold back into the plasma chamber.Type: GrantFiled: August 25, 2017Date of Patent: January 28, 2020Assignee: AIXTRON SEInventors: Stephen Edward Savas, Miguel Angel Saldana, Dan Lester Cossentine, Hae Young Kim, Subramanian Tamilmani, Niloy Mukherjee, M Ziaul Karim
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Publication number: 20190062947Abstract: During a pre-treat process, hydrogen plasma is used to remove contaminants (e.g., oxygen, carbon) from a surface of a wafer. The hydrogen plasma may be injected into the plasma chamber via an elongated injector nozzle. Using such elongated injector nozzle, a flow of hydrogen plasma with a significant radial velocity flows over the wafer surface, and transports volatile compounds and other contaminant away from the wafer surface to an exhaust manifold. A protective liner made from crystalline silicon or polysilicon may be disposed on an inner surface of the plasma chamber to prevent contaminants from being released from the surface of the plasma chamber. To further decrease the sources of contaminants, an exhaust restrictor made from silicon may be employed to prevent hydrogen plasma from flowing into the exhaust manifold and prevent volatile compounds and other contaminants from flowing from the exhaust manifold back into the plasma chamber.Type: ApplicationFiled: August 25, 2017Publication date: February 28, 2019Inventors: Stephen Edward Savas, Miquel Angel Saldana, Dan Lester Cossentine, Hae Young Kim, Subramanian Tamilmani, Niloy Mukherjee, M. Ziaul Karim
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Publication number: 20180347063Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: ApplicationFiled: December 21, 2017Publication date: December 6, 2018Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George Kamian, Jay Ashjaee, Takao Yonehara
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Patent number: 10138565Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: GrantFiled: January 4, 2017Date of Patent: November 27, 2018Assignee: TruTag Technologies, Inc.Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
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Publication number: 20180323087Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: ApplicationFiled: January 4, 2017Publication date: November 8, 2018Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
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Patent number: 9929054Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.Type: GrantFiled: December 14, 2015Date of Patent: March 27, 2018Inventors: Takao Yonehara, Virendra V. Rana, Sean M. Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
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Patent number: 9890465Abstract: This disclosure enables high-productivity controlled fabrication of uniform porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: GrantFiled: December 8, 2014Date of Patent: February 13, 2018Assignee: TruTag Technologies, Inc.Inventors: Karl-Josef Kramer, Mehrdad M. Moslehi, Subramanian Tamilmani, George D. Kamian, Jay Ashjaee, Takao Yonehara
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Patent number: 9869031Abstract: This disclosure enables high-productivity fabrication of semiconductor-based separation layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers), optical reflectors (made of multi-layer/multi-porosity porous semiconductors such as porous silicon), formation of porous semiconductor (such as porous silicon) for anti-reflection coatings, passivation layers, and multi-junction, multi-band-gap solar cells (for instance, by forming a variable band gap porous silicon emitter on a crystalline silicon thin film or wafer-based solar cell). Other applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation).Type: GrantFiled: April 6, 2015Date of Patent: January 16, 2018Assignee: OB Realty, LLCInventors: George D. Kamian, Somnath Nag, Subramanian Tamilmani, Mehrdad M. Moslehi, Karl-Josef Kramer, Takao Yonehara
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Patent number: 9771662Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: GrantFiled: July 6, 2015Date of Patent: September 26, 2017Assignee: OB REALTY, LLCInventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
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Publication number: 20170243767Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: ApplicationFiled: January 4, 2017Publication date: August 24, 2017Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
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Publication number: 20160336233Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.Type: ApplicationFiled: December 14, 2015Publication date: November 17, 2016Inventors: Takao Yonehara, Virendra V. Rana, Sean M. Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
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Publication number: 20160186358Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: ApplicationFiled: July 6, 2015Publication date: June 30, 2016Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara
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Patent number: 9214353Abstract: Methods and systems are provided for the split and separation of a layer of desired thickness of crystalline semiconductor material containing optical, photovoltaic, electronic, micro-electro-mechanical system (MEMS), or optoelectronic devices, from a thicker donor wafer using laser irradiation.Type: GrantFiled: February 26, 2013Date of Patent: December 15, 2015Assignee: Solexel, Inc.Inventors: Takao Yonehara, Virenda V. Rana, Sean Seutter, Mehrdad M. Moslehi, Subramanian Tamilmani
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Publication number: 20150308008Abstract: An apparatus for anodizing substrates immersed in an electrolyte solution. A substrate holder mounted in a storage tank includes a first support unit having first support elements for supporting, in a liquid-tight condition, portions of the substrates, and a second support unit attachable to and detachable from the first support unit and having second support elements for supporting, in a liquid-tight condition, the remaining portions of the substrates. The second support unit includes a first portion second support unit having support elements for supporting first portions of the remaining portions of the surfaces of the substrates, and a second portion second support unit having support elements for supporting second portions of the remaining portions of the surfaces of the substrates.Type: ApplicationFiled: March 30, 2015Publication date: October 29, 2015Inventors: Yasuyoshi MIYAJI, Noriyuki HAYASHI, Takamitsu INAHARA, Takao YONEHARA, Karl-Josef KRAMER, Subramanian TAMILMANI
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Publication number: 20150299892Abstract: It is an object of this disclosure to provide high productivity, low cost-of-ownership manufacturing equipment for the high volume production of photovoltaic (PV) solar cell device architecture. It is a further object of this disclosure to reduce material processing steps and material cost compared to existing technologies by using gas-phase source silicon. The present disclosure teaches the fabrication of a sacrificial substrate base layer that is compatible with a gas-phase substrate growth process. Porous silicon is used as the sacrificial layer in the present disclosure. Further, the present disclosure provides equipment to produce a sacrificial porous silicon PV cell-substrate base layer.Type: ApplicationFiled: January 5, 2015Publication date: October 22, 2015Inventors: Mehrdad M. Moslehi, Doug Crafts, Subramanian Tamilmani, Karl-Josef Kramer, George D. Kamian, Somnath Nag
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Patent number: 9076642Abstract: This disclosure enables high-productivity fabrication of porous semiconductor layers (made of single layer or multi-layer porous semiconductors such as porous silicon, comprising single porosity or multi-porosity layers). Some applications include fabrication of MEMS separation and sacrificial layers for die detachment and MEMS device fabrication, membrane formation and shallow trench isolation (STI) porous silicon (using porous silicon formation with an optimal porosity and its subsequent oxidation). Further, this disclosure is applicable to the general fields of photovoltaics, MEMS, including sensors and actuators, stand-alone, or integrated with integrated semiconductor microelectronics, semiconductor microelectronics chips and optoelectronics.Type: GrantFiled: September 24, 2011Date of Patent: July 7, 2015Assignee: Solexel, Inc.Inventors: Takao Yonehara, Subramanian Tamilmani, Karl-Josef Kramer, Jay Ashjaee, Mehrdad M. Moslehi, Yasuyoshi Miyaji, Noriyuki Hayashi, Takamitsu Inahara