Abstract: Techniques are provided for improving performance of spatial queries by defining a grid that divides the domain space into cells, and then using a cell-to-item mapping to determine which items do not have to be individually evaluated against the location criteria of the spatial queries. Based on the cell to which an item belongs, the item may automatically qualify as a match, be automatically disqualified, or require item-specific evaluation. To account for items with size, the query window of a spatial query may be expanded. To limit the degree to which the query window is expanded, a plurality of grids may be established for the domain space, where each grid has differently sized cells, and items are assigned to grids based on the size of the items.

Abstract: Techniques herein are for generating geometric models. A method involves receiving a raw data set. Generation parameters include an abstraction function, a raw data set, a plurality of size pairs, and a quality interval. Each size pair comprises a view size and a portion size. The view size comprises an amount of display area. The portion size comprises an amount of raw data. For each size pair, associate a set of grid square sizes with the size pair. Each grid square size comprises a multiple of natural units. The quality interval contains a multiplicative product of the grid square size times a ratio of the view size to the portion size. Generate a set of geometric models based on the raw data set, the plurality of size pairs, the abstraction function, and the set of grid square sizes associated with the plurality of size pairs.

Abstract: Techniques herein are for generating geometric models. A method involves receiving a raw data set. Generation parameters include an abstraction function, a raw data set, a plurality of size pairs, and a quality interval. Each size pair comprises a view size and a portion size. The view size comprises an amount of display area. The portion size comprises an amount of raw data. For each size pair, associate a set of grid square sizes with the size pair. Each grid square size comprises a multiple of natural units. The quality interval contains a multiplicative product of the grid square size times a ratio of the view size to the portion size. Generate a set of geometric models based on the raw data set, the plurality of size pairs, the abstraction function, and the set of grid square sizes associated with the plurality of size pairs.

Abstract: A method for calculating voltage values in a power grid, including: obtaining a primary circuit representation (PCR) corresponding to the power grid and including: multiple nodes separated by multiple impedances; and an independent source connected to one node; identifying a high degree node; obtaining a modified circuit representation (MCR) by connecting, in the PCR, an auxiliary voltage source having an auxiliary voltage value to the high degree node, the MCR including a modified characteristic matrix and a modified source vector; calculating a modified state vector based on the modified characteristic matrix and the modified source vector; generating an admittance matrix based on the multiple impedances and the auxiliary voltage; obtaining an auxiliary voltage adjustment value using the admittance matrix; obtaining a primary state vector by adjusting the modified state vector using the admittance matrix and the auxiliary voltage adjustment value; and obtaining the voltage values from the primary state vect

Abstract: A system that simulates an integrated circuit is formed of a plurality of devices. The system initially performs a fundamental circuit simulation run using original parameters for the plurality of devices and an initial time step. The system generates one or more fundamental time steps from the fundamental circuit simulation run. The fundamental time steps are generated when changes that indicate state time derivatives during two or more successive integration steps are within a predetermined range. The system stores the one or more fundamental time steps as fundamental circuit events in an events queue, and updates the parameters for the plurality of devices based on the fundamental circuit events to generate one or more derivative circuits. The system then performs one or more derivative circuit simulation runs using the derivative circuits.

Abstract: A system that simulates an integrated circuit is formed of a plurality of devices. The system initially performs a fundamental circuit simulation run using original parameters for the plurality of devices and an initial time step. The system generates one or more fundamental time steps from the fundamental circuit simulation run. The fundamental time steps are generated when changes that indicate state time derivatives during two or more successive integration steps are within a predetermined range. The system stores the one or more fundamental time steps as fundamental circuit events in an events queue, and updates the parameters for the plurality of devices based on the fundamental circuit events to generate one or more derivative circuits. The system then performs one or more derivative circuit simulation runs using the derivative circuits.

Abstract: Techniques are provided for improving performance of spatial queries by defining a grid that divides the domain space into cells, and then using a cell-to-item mapping to determine which items do not have to be individually evaluated against the location criteria of the spatial queries. Based on the cell to which an item belongs, the item may automatically qualify as a match, be automatically disqualified, or require item-specific evaluation. To account for items with size, the query window of a spatial query may be expanded. To limit the degree to which the query window is expanded, a plurality of grids may be established for the domain space, where each grid has differently sized cells, and items are assigned to grids based on the size of the items.

Abstract: Embodiments of the invention provide systems and methods for parallelizing simulation of circuit partitions. A circuit is divided into a number of partitions, for example, according to channel-connected regions. In some embodiments, the partitions are sequenced and assigned to multiple threads for parallel analysis. Iterative timing analysis (ITA), or some other form of analysis, is performed on the partitions over a series of integration time steps. Using the multiple threads, some partitions are solved at later integration time steps while the ITA continues toward relaxation convergence for a current integration time step.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.

Abstract: Methods for calculating delays for cells in ASICs are disclosed. In the present invention, delays are computed by considering not only the process (P), voltage (V), temperature (T) but also input ramptime (R) and output load or fanout (F) of the cells by fitting the delay at four corner points for derated PVT condition into a non-linear equation which is a function of P, V, T, R and F. Thus, the delay is a five dimensional characterization, and the characterization is split into (P,V,T) characterization and (R,T) characterization to reduce the characterization time and resources. The present invention provides for accurate calculation of delays for cells in ASICs.