Patents by Inventor SUBRAMANYA DULLOOR

SUBRAMANYA DULLOOR has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11681754
    Abstract: Managing connected data, such as a graph data store, includes a computing device with persistent memory and volatile memory. The computing device stores a graph data store with a plurality of nodes and edges in persistent memory. Each of the edges defines the relationship between at least two of the nodes. The nodes and edges may contain tags and properties containing additional information. In response to a search request query, the computing device generates an iterator object stored in volatile memory with a reference to one or more nodes and/or edges in the graph data store. The split between volatile and persistent memory allocation could be used for other objects, such as allocators and transactions. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 26, 2020
    Date of Patent: June 20, 2023
    Assignee: Intel Corporation
    Inventors: Vishakha Gupta, Alain Kagi, Philip Lantz, Subramanya Dulloor
  • Publication number: 20210117473
    Abstract: Managing connected data, such as a graph data store, includes a computing device with persistent memory and volatile memory. The computing device stores a graph data store with a plurality of nodes and edges in persistent memory. Each of the edges defines the relationship between at least two of the nodes. The nodes and edges may contain tags and properties containing additional information. In response to a search request query, the computing device generates an iterator object stored in volatile memory with a reference to one or more nodes and/or edges in the graph data store. The split between volatile and persistent memory allocation could be used for other objects, such as allocators and transactions. Other embodiments are described and claimed.
    Type: Application
    Filed: December 26, 2020
    Publication date: April 22, 2021
    Inventors: Vishakha Gupta, Alain Kagi, Philip Lantz, Subramanya Dulloor
  • Patent number: 10108556
    Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a near memory cache, wherein the near memory cache comprises a cache line comprising an identifier associated with the transaction and a status flag indicating whether the cache line is committed or uncommitted, and a cache controller operatively coupled to the near memory cache to determine, based on the status flag, what operation is to be performed with respect to contents of the cache line.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Rajesh Sankaran, Subramanya Dulloor, Sheng Li
  • Publication number: 20170090807
    Abstract: Managing connected data, such as a graph data store, includes a computing device with persistent memory and volatile memory. The computing device stores a graph data store with a plurality of nodes and edges in persistent memory. Each of the edges defines the relationship between at least two of the nodes. The nodes and edges may contain tags and properties containing additional information. In response to a search request query, the computing device generates an iterator object stored in volatile memory with a reference to one or more nodes and/or edges in the graph data store. The split between volatile and persistent memory allocation could be used for other objects, such as allocators and transactions. Other embodiments are described and claimed.
    Type: Application
    Filed: September 26, 2015
    Publication date: March 30, 2017
    Inventors: Vishakha Gupta, Alain Kagi, Philip Lantz, Subramanya Dulloor
  • Publication number: 20160364340
    Abstract: A processor includes a processing core to execute an application comprising instructions encoding a transaction with a persistent memory via a near memory cache, wherein the near memory cache comprises a cache line comprising an identifier associated with the transaction and a status flag indicating whether the cache line is committed or uncommitted, and a cache controller operatively coupled to the near memory cache to determine, based on the status flag, what operation is to be performed with respect to contents of the cache line.
    Type: Application
    Filed: August 25, 2016
    Publication date: December 15, 2016
    Inventors: SANJAY KUMAR, RAJESH SANKARAN, SUBRAMANYA DULLOOR, SHENG LI
  • Patent number: 9430396
    Abstract: A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: August 30, 2016
    Assignee: Intel Corporation
    Inventors: Sanjay Kumar, Rajesh Sankaran, Subramanya Dulloor, Sheng Li
  • Publication number: 20160179687
    Abstract: A processor includes a processing core to execute an application including instructions encoding a transaction with a persistent memory via a volatile cache that includes a cache line associated with the transaction, the cache line being associated with a cache line status, and a cache controller operatively coupled to the volatile cache, the cache controller, in response to detecting a failure event, to, in response to determining that the cache line status that the cache line is committed, evict contents of the cache line to the persistent memory, and in response to determining that the cache line status indicating that the cache line is uncommitted, discard the contents of the cache line.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Inventors: SANJAY KUMAR, RAJESH SANKARAN, SUBRAMANYA DULLOOR, SHENG LI