Patents by Inventor Subramanya Mayya Kolake

Subramanya Mayya Kolake has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220085620
    Abstract: Disclosed are methods and apparatuses for charging a hybrid battery pack, the method including determining, by a battery management system (BMS), a current split ratio for allocating charging current to an energy cell and a power cell in a hybrid battery pack, based on any one or any combination of a state of charge (SoC) level of the energy cell at an instance of initiation of charging, a SoC level of the power cell at the instance of the initiation of the charging, a wattage of an adapter for charging the hybrid battery pack, a capacity of the hybrid battery pack, and a charging time period, and charging, by the BMS, the hybrid battery pack by allocating the charging current to the energy cell and the power cell based on the current split ratio.
    Type: Application
    Filed: August 16, 2021
    Publication date: March 17, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Shashishekara Parampalli ADIGA, Mohan Kumar Singh VERMA, Ashish KHANDELWAL, Krishnan S HARIHARAN, Rajkumar Subhash PATIL, Subramanya Mayya KOLAKE
  • Patent number: 8125131
    Abstract: Provided are a nano filament structure and a method of forming the nano filament structure. The nano filament structure includes a first layer disposed on a substrate, a second layer having a gap of nanometer size disposed on the first layer, a catalyst layer interposed between the first layer and the second layer, and a nano filament. One end of the nano filament is in contact with the catalyst layer and grows by penetrating the gap of the second layer.
    Type: Grant
    Filed: June 18, 2009
    Date of Patent: February 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Subramanya Mayya Kolake, In-Seok Yeo, Xiao Feng Wang
  • Patent number: 7915668
    Abstract: A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of storing at least one charge. The charge storage elements can include fullerenes.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: March 29, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Subramanya Mayya Kolake, In-Seok Yeo, Kyong-Hee Joo
  • Patent number: 7659624
    Abstract: A semiconductor device includes a substrate, an insulating layer having an opening, the opening exposing a portion of the substrate, a hydrophobic layer covering substantially only a sidewall and a top surface of the insulating layer, and a nanoscale conductive structure on the exposed portion of the substrate.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co,., Ltd.
    Inventors: Subramanya Mayya Kolake, Sun-Woo Lee, In-Seok Yeo
  • Publication number: 20090322200
    Abstract: Provided are a nano filament structure and a method of forming the nano filament structure. The nano filament structure includes a first layer disposed on a substrate, a second layer having a gap of nanometer size disposed on the first layer, a catalyst layer interposed between the first layer and the second layer, and a nano filament.
    Type: Application
    Filed: June 18, 2009
    Publication date: December 31, 2009
    Inventors: Subramanya Mayya Kolake, In-Seok Yeo, Xiao Feng Wang
  • Publication number: 20080157363
    Abstract: A method of forming a nanoscale structure includes providing a substrate having a first layer thereon, the first layer having an opening that exposes a region of the substrate, and contacting the substrate with a catalytic material, wherein the exposed region of the substrate has a first property that attracts the catalytic material, and the first layer has a second property that repels the catalytic material.
    Type: Application
    Filed: April 16, 2007
    Publication date: July 3, 2008
    Inventors: Subramanya Mayya Kolake, Sun-Woo Lee, In-Seok Yeo
  • Publication number: 20080096306
    Abstract: A memory device includes an insulating layer formed over a substrate, a gate formed over the insulating layer, and charge storage elements disposed over the insulating layer. The charge storage elements are separated from each other and are electrically insulated, and each of the charge storage elements is capable of storing at least one charge. The charge storage elements can include fullerenes.
    Type: Application
    Filed: January 31, 2007
    Publication date: April 24, 2008
    Inventors: Subramanya Mayya Kolake, In-Seok Yeo, Kyong-Hee Joo