Abstract: A method of metallization comprising forming a conductive layer comprising nickel and vanadium inside an opening. The conductive layer comprising nickel and vanadium can be used as a barrier layer to prevent interlayer metal diffusion. Alternatively, the conductive layer can also be used as a seed layer for subsequent metal electroplating. In one embodiment, the conductive layer is used as an integrated barrier and seed layer for subsequent copper plating for submicron applications.

Abstract: A method for polishing a metal layer (20) containing a combination of wide features (12), low density features (14), and high density features (18), is illustrated. A hydrophilic polish pad (24) having a shore D hardness of greater than 50 is used along with slurry (22) containing silica and an acidic based oxidizer such as oxadic acid in a chemical mechanical polishing (CMP) process. The result is less than 5:1 and preferably 1:1. This low selectivity results in the metal layer (20) being polished to a level below the surface of the surrounding oxide in a timed-controlled polish.

Abstract: A pattern of dummy structures (20) is added to the layout pattern of an integrated circuit (10) to equilibrate the polishing rate across the surface of a semiconductor substrate (11). The location of each dummy structure (20) is predetermined so that it does not intersect a well boundary (17) or an active region (21,27), and does not fall under a conductive material such as a layer of polysilicon (22,28) or an interconnect structure (23,29).

Abstract: A polishing system (10) is used to polish a semiconductor wafer (16) in accordance with the present invention. Polishing system (10) includes a wafer carrier (14) which includes a modulation unit (20). Modulation unit (20) includes a plurality of capacitors made up of a flexible lower plate (22) and a plurality of smaller upper plate segments (24). A controller (40) monitors the capacitance between each smaller upper plate segment (24) and lower plate (22), and compares the measured capacitance against a predefined set capacitance. To the extent the measured capacitance and predefined capacitance are different, controller (40) adjusts the voltage being applied to the respective upper plate segment (24) so that the measured capacitance and predefined capacitance are aligned. Thus, the present invention is able to achieve dynamic and localized control of the shape of the wafer as it is being polished.