Abstract: A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.

Abstract: A bus bridge between a high speed DMA bus and a lower speed peripheral bus sets a threshold for minimum available buffer space to send a read request dependent upon a frequency ratio and the DMA read latency. Similarly, a threshold for minimum available data for a write request depends on the frequency ratio and the DMA write latency. The bus bridge can store programmable values for the DMA read latency and write latency.

Abstract: A system-on-chip integrated circuit selectively gates clocks to individual modules corresponding to the state of a corresponding bit of a peripheral enable register. A reset circuit supplies a signal to a reset input of the digital module for a normal mode if the bit indicates the power-up state and a reset mode if the bit indicates a power-down state. Return to normal mode is delayed a predetermined time after the said bit of indicates the power-up state to ensure clean power up. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the corresponding bit indicates the power-down state.

Abstract: A system-on-chip integrated circuit includes a peripheral initialization register has a bit corresponding to each module. Each bit indicates a normal mode or a reset mode for the corresponding module. A direct memory access unit can receive, prioritize and queue date movement transactions between modules and can read from or write to the peripheral initialization register. A peripheral interface unit prevents a write to the peripheral initialization register changing a module from reset mode to normal mode while there is an uncompleted data movement transaction involving that module. A false acknowledge circuit for each module supplies an acknowledge signal in response to a received command if the module is in reset mode.

Abstract: A methodology for automatic validation of integrated circuit (IC) test hardware that is performed during extraction of the test hardware. Signal connectivity between output test ports of one or more test control blocks and serially-connected scan latches of the test hardware is automatically validated, as is inter-connectivity between the serially-connected scan latches. Every instance to which a test signal and a test data signal at an output test port (both test signal and test data ports) of a test control block fans out to is traversed until a scan latch is reached in order to provide electrical and functional verification of the test hardware.