Abstract: Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is as follows: (i) receiving a first memory location that is subject to a miscompare between an associated simulation value for the first memory location and an associated actual value for the first memory location; (ii) backtracking through instructions of a test case to determine the identity of a set of backtrack locations upon which the first memory location is dependent, with the set of backtrack locations being made up of at least one of: memory locations and register locations; and (iii) comparing respective simulation values and actual values for at least one of the backtrack locations to help determine a cause of the miscompare at the first memory location.

Abstract: Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.

Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.

Abstract: Debugging techniques performed post-silicon, but with reference to pre-silicon phase data and/or reference model data. For example, one debugging technique is as follows: (i) receiving a first memory location that is subject to a miscompare between an associated simulation value for the first memory location and an associated actual value for the first memory location; (ii) backtracking through instructions of a test case to determine the identity of a set of backtrack locations upon which the first memory location is dependent, with the set of backtrack locations being made up of at least one of: memory locations and register locations; and (iii) comparing respective simulation values and actual values for at least one of the backtrack locations to help determine a cause of the miscompare at the first memory location.

Abstract: Using an “optimized” test case for testing hardware and/or software of a computer. The optimized test case is designed to be run on a data storage device including multiple read locations and multiple write locations. Initialization data is written, on the data storage device, only to the write locations of the data storage device. The optimized test case is run on the data storage device in a manner so that the optimized test case will only write data to each write location after that write location has had initialization data written to that write location. The optimized test case defines read locations and write locations so that, during running of the optimized test case, all read locations which are also write locations will be written by a write instruction of the test case before being read by a read instruction of the test case.

Abstract: By arranging dies in a stack such that failed cores are aligned with adjacent good cores, fast connections between good cores and cache of failed cores can be implemented. Cache can be allocated according to a priority assigned to each good core, by latency between a requesting core and available cache, and/or by load on a core.

Abstract: A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index.

Abstract: A data processing system, method and computer program product to receive general-purpose code for iterative summation of an aggregate number of addends, wherein each addend has a precision. The data processing system operates an arithmetic hardware unit to set a first set of input registers to be a target of memory mapped registers and uses a broad-based adder to generate an adder result, wherein the broad-based adder has a broad-based adder size of inputs, and the broad-based adder size is less than the aggregate number of addends and greater than two, wherein each input register of the first set of input registers is connected to each input. Further, the data processing system may write the adder result to a storage array in memory, wherein the adder result is the sum of the inputs, and the adder result is placed in the storage array as indexed by a storage array index.