Patents by Inventor Subrat Mohapatra

Subrat Mohapatra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220305000
    Abstract: The present disclosure relates to the field of oncology and particularly towards a combination therapy for treatment of cancer. In particular, the present disclosure provides a combination therapy comprising chloroquine, metformin and statin, for treatment/management of Myeloproliferative neoplasms (MPNs) or any associated condition. The combinations of the present disclosure show a synergistic cytotoxic activity against cancer cells. The present disclosure also relates to a composition comprising said combination, and a method for treatment/management of MPN or any associated condition by employing said composition or combination therapy. The present disclosure also provides combination of chloroquine, metformin and statin for use in treatment/management of MPN or any associated condition.
    Type: Application
    Filed: March 23, 2022
    Publication date: September 29, 2022
    Inventors: Ansu Kumar, Swati Khandelwal, Subrat Mohapatra, Himanshu Grover, Vivek Patil, Anuj Tyagi, Ashish Kumar Agrawal, Shweta Kapoor, Yatin Mundkur
  • Patent number: 7639045
    Abstract: A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: December 29, 2009
    Assignee: Intersil Americas Inc.
    Inventors: Ali Motamed, Subrat Mohapatra
  • Publication number: 20090289693
    Abstract: A bi-directional buffer includes at least a first and second pair of one-shots and transistors. At least the first pair of one-shots and the first pair of transistors enable a second input/output (I/O) terminal to follow a first I/O terminal. At least the second pair of one-shots and the second pair of transistors enable the first I/O terminal to follow the second I/O terminal. There is a detection of whether the direction of a signal is from the first I/O terminal to second I/O terminal, or vise versa. If the direction is from the first I/O terminal to the second I/O terminal, there is an at least temporarily disabling the second pair of one-shots to thereby reduce feedback that may occur from the second I/O terminal to the first I/O terminal. If the direction is from the second I/O terminal to the first I/O terminal, there is an at least temporarily disabling the first pair of one-shots to thereby reduce feedback that may occur from the first I/O terminal to the second I/O terminal.
    Type: Application
    Filed: July 22, 2008
    Publication date: November 26, 2009
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Ali Motamed, Subrat Mohapatra
  • Patent number: 5990749
    Abstract: A novel device for pole splitting which can be employed in multistage amplifiers having a final stage and a prior stage. The device comprises a first capacitor connected between the output of the prior stage and the output of the final stage, a source follower, and a second capacitor connected between the output of the prior stage and the source follower. The source follower provides an offset voltage that reduces variation of the total capacitance of the first and second capacitors. In a preferred version of the present invention, the first and second capacitor each comprise a MOSFET transistor having a certain threshold voltage. The offset voltage is set to be at least the threshold voltage of the MOSFET transistors. In a preferred version, the source follower comprises a plurality of MOSFET transistors, which includes a MOSFET transistor having a gate connected to the first capacitor and a source connected to the second capacitor.
    Type: Grant
    Filed: December 9, 1997
    Date of Patent: November 23, 1999
    Assignee: LSI Logic Corporation
    Inventors: Subrat Mohapatra, Edward Liu