Abstract: Systems, methods, and apparatuses relating to circuitry to implement a multiprocessor boot flow for a faster boot process are described. In one embodiment, a system includes a hardware processor comprising a processor core, a cache coupled to the hardware processor, storage for hardware initialization code, and a controller circuit to initialize a portion of the cache as memory for usage by the hardware initialization code before beginning execution of the hardware initialization code after a power on of the system.

Abstract: During a computing system boot sequence, reference firmware provided by a computing system component supplies Advanced Component and Peripheral Interface (ACPI) code that generates ACPI tables and definition blocks to a bootloader. During a boot sequence, the reference firmware receives an indication from the bootloader which components the reference firmware is to initialize. As part of component initialization performed by the reference firmware, the reference firmware populates hand-off data structures (e.g., hand-off blocks (HOBs)) with ACPI code (AML code) that, when executed by the bootloader, generates and populates ACPI tables (e.g., DSDT and SSDT tables) and definition blocks with information pertinent to the initialization and runtime management of computing system components. Component initialization and runtime configuration workarounds can be implemented in the bootloader incorporating reference firmware updates provided by the component vendor.

Abstract: Systems, apparatuses and methods may provide for technology that identifies, during a first boot process, whether at least one task associated with at least one software program is set to occur in a single-threaded process or a multithreaded process, in response to the at least one task being set to occur in the multithreaded process, executing the at least one task in the multithreaded process during the first boot process, and in response to the at least one task being set to occur in the single-threaded process, executing the at least one task in the single-threaded process during the first boot process.

Abstract: Systems, apparatuses and methods may provide for technology that detects a low battery condition in a computing system including an integrated graphics processor and a discrete graphics processor, wherein the low battery condition is detected during a pre-boot stage of the computing system. The technology may also disable a root port associated with the discrete graphics processor in response to the low battery condition, conduct an initialization of an integrated display while the root port is disabled, and enable the root port in response to a successful negotiation of increased power by a verified read write code of an embedded controller of the computing system.

Abstract: Systems, apparatuses and methods may provide for technology that initializes static random access memory (SRAM) of a processor in response to a reset of the processor, allocates the SRAM to one or more security enforcement operations, and triggers a multi-threaded execution of the one or more security enforcement operations before completion of a basic input output system (BIOS) phase. In one example, the multi-threaded execution is triggered independently of a dynamic RAM (DRAM) initialization.

Abstract: Embodiments are directed to a phased boot process to dynamically initialize devices in a verified environment. An embodiment of a system includes a memory device to store platform initialization firmware to cause the processing system to: initialize, during a boot process, a portion of the one or more memory modules as system management random access memory (SMRAM) for system management mode (SMM) usage; generate an SMM component in the SMRAM, the SMM component comprising an SMM handler routine to handle dynamic intellectual property (IP) management operations corresponding to the plurality of hardware components; register the SMM handler routine with an SMM interrupt (SMI) for identification of SMM events from an operating system (OS); and generate an SMM dispatcher in the SMRAM, the SMM dispatcher to create an instance of the SMM handler routine in the SMRAM in response to receiving an SMI from the OS during runtime of the processing system.

Abstract: Embodiments are directed to improving boot process for early display initialization and visualization. An embodiment of a system includes a plurality of processor cores; a cache coupled to the plurality of processor cores; and a controller circuit to: initialize a portion of the cache as static memory for hardware initialization code usage before beginning execution of the hardware initialization code after a power on of the hardware processor; and cause initialization of a display device to be performed using the portion of the cache, the initialization of the display device performed independently of initialization of dynamic memory of the hardware processor.

Abstract: Systems, apparatuses and methods may provide for technology that initiates a boot of a computing system containing an embedded controller while the computing system is in a low power mode, conducts a verification that code to perform the boot is uncorrupted, and negotiates an increased power delivery with a source device connected to the computing system if the verification is successful.