Abstract: The present disclosure discloses a digital communication between the embedded cable modem (eCM) and embedded set-top box (eSTB) via a shared memory. The communication is carried out by packet transfer mechanism as per the protocol without adding any extra header overhead. The communication link is established between the eSTB and eCM mainly in layer 2 and partly in layer 1 according to an implementation of the OSI model. Further, eSTB is used as an eSAFE device coupled to eCM where the eCM and eSTB are considered to be placed on two SoCs with a separate CPU to each SoC (System-On-Chip) with a shared memory (via high speed data bus protocol). DMA (Direct Memory Access) engines are used to accelerate data transfer and to reduce load. DMA of only eCM, SoC is used to minimize hardware resources.

Abstract: The present disclosure discloses a digital communication between the between embedded cable modem (eCM) and embedded set-top box (eSTB) via a shared memory. The communication is carried out by packet transfer mechanism as per the protocol without adding any extra header overhead. The communication link is established between the eSTB and eCM mainly in layer 2 and partly in layer 1 according to an implementation of the OSI model. Further, eSTB is used as an eSAFE device coupled to eCM where the eCM and eSTB are considered to be placed on two SoCs with a separate CPU to each SoC (System-On-Chip) with a shared memory (via high speed data bus protocol). DMA (Direct Memory Access) engines are used to accelerate data transfer and to reduce load. DMA of only eCM, SoC is used to minimize hardware resources.

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs.

Abstract: A system for clock recovery in digital video communication includes a delay measurement block for generating PCR input signals and for continuously determining the time interval between successive PCR input signals. The system also includes a first storage device for generating a first PCR signal corresponding to the time interval between arrival of successive PCR input signals and a PCR inter-arrival time computation filtering device to determine the average time of arrival difference between successive PCR packets. The system further includes an error correction device for minimizing error in the average PCR difference between successive PCR packets, a controlled system clock generator coupled to the output of the error correction device to generate system clock, a second storage device for generating a first system clock output, and a controlled clock period difference computation element for computing the clock period difference between the first and second system clock outputs.