Patents by Inventor Su-chang Lee

Su-chang Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12132009
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: October 29, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Su Chang Lee
  • Publication number: 20240290750
    Abstract: A semiconductor package includes a substrate including a first region having a recess defined therein and a second region spaced apart from the first region. The second region does not include the recess. A three-dimensional (3D) integrated circuit structure is on the first region. The 3D integrated circuit structure includes a first semiconductor chip die and a second semiconductor chip die disposed on the first semiconductor chip die. A plurality of connecting members electrically connecting the first semiconductor chip die to the substrate. A first side of each connecting member of the plurality of connecting members directly contacts the first semiconductor chip die and a second side that is opposite to the first side directly contacts the first region. A memory structure is disposed in the second region and positioned side by side with the 3D integrated circuit structure.
    Type: Application
    Filed: September 13, 2023
    Publication date: August 29, 2024
    Inventors: Hyoeun LEE, Hyunggil BAEK, Su-Chang LEE, Gyunghwan OH
  • Publication number: 20230275036
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Application
    Filed: May 5, 2023
    Publication date: August 31, 2023
    Inventor: Su Chang LEE
  • Patent number: 11646275
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Grant
    Filed: July 14, 2021
    Date of Patent: May 9, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Su Chang Lee
  • Publication number: 20210343660
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Application
    Filed: July 14, 2021
    Publication date: November 4, 2021
    Inventor: Su Chang LEE
  • Patent number: 11088091
    Abstract: A semiconductor package includes a substrate having first and second surfaces, first and second pads disposed on the first and second surfaces respectively and electrically connected to each other, a semiconductor chip disposed on the first surface and connected to the first pads, a dummy chip disposed on the first surface, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate, an underfill between the semiconductor chip and the first surface of the substrate with an extension portion extended along facing side surfaces of the semiconductor chip and the dummy chip in the perpendicular direction, an upper end of the extension portion lower than the upper surface of the semiconductor chip, and a sealing material on the first surface to seal the semiconductor chip and the dummy chip.
    Type: Grant
    Filed: May 5, 2020
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Su Chang Lee
  • Publication number: 20200266156
    Abstract: A semiconductor package includes a substrate having first and second surfaces, first and second pads disposed on the first and second surfaces respectively and electrically connected to each other, a semiconductor chip disposed on the first surface and connected to the first pads, a dummy chip disposed on the first surface, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate, an underfill between the semiconductor chip and the first surface of the substrate with an extension portion extended along facing side surfaces of the semiconductor chip and the dummy chip in the perpendicular direction, an upper end of the extension portion lower than the upper surface of the semiconductor chip, and a sealing material on the first surface to seal the semiconductor chip and the dummy chip.
    Type: Application
    Filed: May 5, 2020
    Publication date: August 20, 2020
    Inventor: Su Chang LEE
  • Patent number: 10651133
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: May 12, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Su Chang Lee
  • Publication number: 20190237412
    Abstract: A semiconductor package includes a substrate having a first surface and a second surface opposing the first surface; a plurality of first pads disposed on the first surface of the substrate and a plurality of second pads disposed on the second surface of the substrate and electrically connected to the plurality of first pads; a semiconductor chip disposed on the first surface of the substrate and connected to the plurality of first pads; a dummy chip having a side surface facing one side surface of the semiconductor chip, disposed on the first surface of the substrate spaced apart from the semiconductor chip in a direction parallel to the first surface of the substrate, the dummy chip having an upper surface positioned lower than an upper surface of the semiconductor chip in a direction perpendicular to the first surface of the substrate; an underfill disposed between the semiconductor chip and the first surface of the substrate, and having an extension portion extended along the facing side surfaces of the s
    Type: Application
    Filed: August 29, 2018
    Publication date: August 1, 2019
    Inventor: Su Chang LEE
  • Patent number: 9698088
    Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.
    Type: Grant
    Filed: April 21, 2016
    Date of Patent: July 4, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heungkyu Kwon, Kang Joon Lee, JaeWook Yoo, Su-Chang Lee
  • Patent number: 9601458
    Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
    Type: Grant
    Filed: March 13, 2014
    Date of Patent: March 21, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Su-chang Lee
  • Publication number: 20160240509
    Abstract: Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.
    Type: Application
    Filed: April 21, 2016
    Publication date: August 18, 2016
    Inventors: Heungkyu KWON, Kang Joon LEE, JaeWook YOO, Su-Chang LEE
  • Patent number: 9048168
    Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.
    Type: Grant
    Filed: November 19, 2013
    Date of Patent: June 2, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Seok-won Lee, Hyon-chol Kim, Su-chang Lee, Chi-young Lee
  • Patent number: 9040351
    Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.
    Type: Grant
    Filed: July 24, 2014
    Date of Patent: May 26, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-Kyu Kwon, Jae-Wook Yoo, Hyon-Chol Kim, Su-Chang Lee, Min-Ok Na
  • Publication number: 20140335657
    Abstract: A stack package includes a lower package including a lower package substrate and a lower semiconductor chip disposed on the lower package substrate, an upper package including an upper package substrate and an upper semiconductor chip disposed on the upper package substrate, a fastening element formed between a top surface of the lower semiconductor chip and a bottom surface of the upper package substrate, and a halogen-free inter-package connector connecting the lower package substrate to the upper package substrate.
    Type: Application
    Filed: July 24, 2014
    Publication date: November 13, 2014
    Applicant: Samsung Electronics Co., Ltd
    Inventors: HEUNG-KYU KWON, JAE-WOOK YOO, HYON-CHOL KIM, SU-CHANG LEE, MIN-OK NA
  • Publication number: 20140193951
    Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
    Type: Application
    Filed: March 13, 2014
    Publication date: July 10, 2014
    Inventors: Heung-kyu Kwon, Su-chang Lee
  • Patent number: 8716872
    Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
    Type: Grant
    Filed: August 19, 2013
    Date of Patent: May 6, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Su-chang Lee
  • Publication number: 20140077382
    Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.
    Type: Application
    Filed: November 19, 2013
    Publication date: March 20, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Seok-won Lee, Hyon-chol Kim, Su-chang Lee, Chi-young Lee
  • Publication number: 20130334708
    Abstract: A stacked semiconductor package has a first semiconductor package including a first package substrate and a first semiconductor chip mounted on the first package substrate, a second semiconductor package including a second package substrate and a second semiconductor chip mounted on the second package substrate, and a plurality of connections electrically connecting the first and second semiconductor packages. The connections are disposed on an outer region of the first package substrate outside the first semiconductor chip. The connections are disposed along opposite first longer sides and opposite shorter second sides of the first package substrate. The heights of those connections disposed along each longer first side gradually vary from a central to an outer region (i.e., the ends) of the longer first side.
    Type: Application
    Filed: August 19, 2013
    Publication date: December 19, 2013
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Heung-kyu Kwon, Su-chang Lee
  • Patent number: 8604614
    Abstract: A semiconductor package can include a substrate body having a first surface and a second surface. A semiconductor chip can be mounted on the first surface and a plurality of electrode pads can be on the second surface and selectively formed to have progressively smaller or larger sizes extending from a central region of the substrate body toward an outer edge of the substrate body based on a reflow soldering process warpage profile for the semiconductor package.
    Type: Grant
    Filed: March 28, 2011
    Date of Patent: December 10, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Heung-kyu Kwon, Seok-won Lee, Hyon-chol Kim, Su-chang Lee, Chi-young Lee