Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A sensor package, a sensor system, and a method for fabricating the sensor package are described that include a sensing chip having dispense chemistry disposed over an array of conductive elements. In an implementation, the sensor package may include a sensing chip that may include at least one conductive element, wherein the at least one conductive element may be part of an array of conductive elements defining a M by N matrix, where M is a number of rows of the at least one conductive element and N is a number of columns of the at least one conductive element. The sensing chip may further include dispense chemistry that may be disposed on the at least one conductive element and at least one contact pad. The sensor package may further include a microfluidic cap that may be positioned over at least a portion of the sensing chip, wherein the microfluidic cap and the sensing chip may define a cavity that may be configured to receive a fluid sample.

Abstract: Self-aligned FET devices and associated fabrication methods are disclosed herein. A disclosed process for forming a FET includes forming a first mask, implanting a deep well region in a drift region using the first mask, forming a spacer in contact with the first mask, and implanting a shallow well region in the drift region using the first mask and the spacer. A disclosed FET includes a drift region, a shallow well region, a deep well region located between the shallow well region and the drift region, and a junction field effect region: in contact with the shallow well region, the drift region, and the deep well region; and having a junction field effect doping concentration of the first conductivity type. The FETs can include a hybrid channel formed by a portion of the junction field effect region, as influenced by the deep well region, and the shallow well region.

Abstract: Semiconductor devices and associated fabrication methods are disclosed. In one disclosed approach a process for forming a semiconductor device is provided. The process includes: implanting a first region of semiconductor material using a first channeled implant with a first conductivity type; and implanting, after the first channeled implant, a second region of semiconductor material using a second channeled implant with a second conductivity type. The first channeled implant disrupts a crystal structure of the first region of semiconductor material and does not disrupt a crystal structure of the second region of semiconductor material.

Abstract: Self-aligned FET devices and associated fabrication methods are disclosed herein. A disclosed process for forming a FET includes forming a first mask, implanting a deep well region in a drift region using the first mask, forming a spacer in contact with the first mask, and implanting a shallow well region in the drift region using the first mask and the spacer. A disclosed FET includes a drift region, a shallow well region, a deep well region located between the shallow well region and the drift region, and a junction field effect region: in contact with the shallow well region, the drift region, and the deep well region; and having a junction field effect doping concentration of the first conductivity type. The FETs can include a hybrid channel formed by a portion of the junction field effect region, as influenced by the deep well region, and the shallow well region.

Abstract: Vertical diodes are disclosed herein for radiation-environment applications. The diodes can be junction barrier Schottky (JBS) diodes. A disclosed vertical diode includes a first region with a first conductivity type, fingers with a second conductivity type and located in a top portion of the first region, at least one tap region with the first conductivity type formed in the fingers, and a metal layer located over and in contact with the first region and the fingers and forming a Schottky barrier with the first region. Another disclosed vertical diode includes a first region with a first conductivity type, fingers with a second conductivity type located in a top portion of the first region and having a well doping concentration, and a metal layer located over the first region and the fingers and forming a Schottky barrier with the first region.

Abstract: The present disclosure describes vertical transistor device and methods of making the same. The vertical transistor device includes substrate layer of first conductivity type, drift layer of first conductivity type formed over substrate layer, body region of second conductivity type extending vertically into drift layer from top surface of drift layer, source region of first conductivity type extending vertically from top surface of drift layer into body region, dielectric region including first and second sections formed over top surface, buried channel region of first conductivity type at least partially sandwiched between body region on first side and first and second sections of dielectric region on second side opposite to first side, gate electrode formed over dielectric region, and drain electrode formed below substrate layer. Dielectric region laterally overlaps with portion of body region. Thickness of first section is uniform and thickness of second section is greater than first section.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JFET also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A semiconductor wafer processing method, having: ablating a back side of a semiconductor wafer with a laser ablation process; and etching the back side of the semiconductor wafer with an etching process; wherein the laser ablation process forms a pattern in the back side of the semiconductor wafer; wherein the etching process preserves the pattern in the back side of the semiconductor wafer.

Abstract: A method of fabricating a wide bandgap device includes providing a thin native substrate. An epitaxial layer is grown on a surface of the native substrate. After growing the epitaxial layer, a handle substrate is attached to the opposite surface of the native substrate by way of an interface layer. With the handle substrate providing mechanical support, wide bandgap devices are fabricated in the epitaxial layer using a low-temperature fabrication process. The handle substrate is detached from the native substrate after fabrication of the wide bandgap devices.

Abstract: A sensor system includes an assay chamber configured to receive a fluid sample. Dispense chemistry disposed within the assay chamber. A first electrode structure includes at least one conductive element and a second electrode structure proximate to the first electrode structure is configured to transmit an electrical signal through the fluid sample. The first electrode structure is configured to receive the electrical signal transmitted through the fluid sample and responsively generate a sense signal. The sense signal being indicative of an interaction of the fluid sample with the dispense chemistry. A controller is electrically coupled to the first electrode structure and configured to identify at least one analyte in the fluid sample based on at least the sense signal generated by the first electrode structure. The first electrode structure is embedded within a base substrate and the second electrode structure is embedded within a microfluidic cap that is coupled to the base substrate.

Abstract: Junction field effect transistors (JFETs) and related manufacturing methods are disclosed herein. A disclosed JFET includes a vertical channel region located in a mesa and a first channel control region located on a first side of the mesa. The first channel control region is at least one of a gate region and a first base region. The JEFT also includes a second base region located on a second side of the mesa and extending through the mesa to contact the vertical channel region. The vertical channel can be an implanted vertical channel. The vertical channel can be asymmetrically located in the mesa towards the first side of the mesa.

Abstract: A sensor package, a sensor system, and a method for fabricating the sensor package are described that include a sensing chip having dispense chemistry disposed over an array of conductive elements. In an implementation, the sensor package may include a sensing chip that may include at least one conductive element, wherein the at least one conductive element may be part of an array of conductive elements defining a M by N matrix, where M is a number of rows of the at least one conductive element and N is a number of columns of the at least one conductive element. The sensing chip may further include dispense chemistry that may be disposed on the at least one conductive element and at least one contact pad. The sensor package may further include a microfluidic cap that may be positioned over at least a portion of the sensing chip, wherein the microfluidic cap and the sensing chip may define a cavity that may be configured to receive a fluid sample.

Abstract: A sensor system includes an assay chamber configured to receive a fluid sample. Dispense chemistry disposed within the assay chamber. A first electrode structure includes at least one conductive element and a second electrode structure proximate to the first electrode structure is configured to transmit an electrical signal through the fluid sample. The first electrode structure is configured to receive the electrical signal transmitted through the fluid sample and responsively generate a sense signal. The sense signal being indicative of an interaction of the fluid sample with the dispense chemistry. A controller is electrically coupled to the first electrode structure and configured to identify at least one analyte in the fluid sample based on at least the sense signal generated by the first electrode structure. The first electrode structure is embedded within a base substrate and the second electrode structure is embedded within a microfluidic cap that is coupled to the base substrate.

Abstract: A capacitive sensor element includes a substrate with a metal pillar disposed upon on the substrate. The metal pillar includes a first end that faces towards the substrate and a second end that faces away from the substrate. An encapsulant is disposed upon the substrate, covering at least one side portion of the metal pillar and extending beyond the second end of the metal pillar. A metal plug is disposed in a cavity defined within the encapsulant. The cavity is defined proximate to the second end of the metal pillar, and the metal plug is in contact with the second end of the metal pillar. The capacitive sensor element also includes a dielectric layer disposed upon the encapsulant, such that the dielectric layer covers the cavity.

Abstract: A semiconductor device including a VDMOS device formed therein includes a terminal, or contact, to the drain region of the VDMOS device from the frontside of the device. In one or more implementations, a semiconductor device includes a semiconductor substrate having a first surface and a second surface and a vertical diffused metal-oxide-semiconductor device formed within the semiconductor substrate. The vertical diffused metal-oxide-semiconductor device includes at least one source region formed proximate to the first surface and at least one drain region formed proximate to the second surface. A through-substrate via is formed within the semiconductor substrate, and the through-substrate via electrically connected to the drain region. The through-substrate via provides an electrical interconnection to the drain region from the first surface.

Abstract: Semiconductor devices, such as laterally diffused metal oxide semiconductor (LDMOS) devices, are described that have a field plate connected to a gate of the device. In one or more implementations, the semiconductor devices include a substrate having a source region of a first conductivity type and a drain region of the first conductivity type. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow majority carriers to travel between the source region and the drain region. The device also includes a field plate at least partially positioned over and connected to the gate. The field plate is configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.

Abstract: A semiconductor device is described that includes a first electrical circuit and a second electrical circuit formed on a semiconductor on insulator wafer. The semiconductor on insulator wafer has a layer of semiconducting material formed over a buried layer of insulating material formed over a supporting layer of material. A wide deep trench is formed in the semiconductor on insulator wafer to galvanically isolate the first electrical circuit from the second electrical circuit. The first electrical circuit and the second electrical circuit are coupled together for exchanging energy between the galvanically isolated electrical circuits.

Abstract: Semiconductor devices, such as LDMOS devices, are described that include an interlayer-dielectric layer (ILD) region having a thickness of at least two and one half (2.5) microns to increase the maximum breakdown voltage. In one or more implementations, the semiconductor devices include a substrate having a source region and a drain region formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. An ILD region having a thickness of at least two and one half (2.5) microns is formed over the surface and the gate of the device. The device also includes one or more field plates configured to shape an electrical field generated between the source region and the drain region when a voltage is applied to the gate.