Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

Abstract: A decoder includes multiple decode gates, each to provide one bit of a decoded output signal. At least two of the decode gates share a transistor. According to one aspect, each of the multiple decode gates is a skewed gate.

Abstract: A low power memory bit line precharge scheme. A memory bit line is coupled to a first read precharge device. A second write precharge device is also coupled to the memory bit line and is to be enabled only in response to a memory write operation.

Abstract: A multi-entry register file cell includes multiple memory elements. A value stored in each of the multiple memory elements may be individually read from the register file cell in response to asserting a single word line.

Abstract: A memory includes a plurality of banks of memory elements. For a memory read access operation, bank enable logic coupled to each of the plurality of banks is responsive to an address of a memory element to be read to selectively deactivate a first precharge clock signal to be received by a first one of the banks that includes the memory element to be read. The bank enable logic is further responsive to the address to selectively maintain in an active state a second precharge clock signal to be received by a second one of the banks that does not include the memory element to be read.

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. The shared pull-up transistor may be used to precharge an output node of the circuit. This circuit may be found useful in clock buffering applications.

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract: A technique for reducing power consumption in a data storage device consisting of a number of data cells includes arranging the number of data cells in clusters, each cluster having more than one data cell having their data enable inputs connected together. A data write bus is provided to provide data enable signals to the data enable inputs of the number of data cells. A number of pass gates are respectively disposed between the clusters and the write data bus. The pass gates are selectively enabled to allow data enable signals to pass from the write data bus to the data enable inputs of the more than one data cell of a selected one or more of the clusters. A number of inverters may be respectively disposed between the number of pass gates and the clusters. A number of sustainer circuits may be respectively connected to the number of pass gates. Each of the pass gates may include a pair of field effect transistors which may be complementary field effect transistors.

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract: A technique for reducing soft errors in a dynamic circuit. For one embodiment, a dynamic circuit includes a dynamic logic gate having an output node at which a logical output value of the logic gate is detected. A keeper circuit coupled to the output node is configured to harden the dynamic circuit by increasing the critical charge at the output node.

Abstract: A circuit for adding two or more numbers and generating a sum and carry output is disclosed. The adder circuit receives two or more numbers to be added together. The adder circuit includes a number of exclusive-or logic circuits that generate intermediate outputs. The intermediate outputs are input to a domino multiplexer. The domino multiplexer includes a multiplexer gate and an exclusive-or gate connected in parallel. The domino multiplexer circuit outputs a sum value and a carry value for the input numbers. A clock signal drives the multiplexer gate and the exclusive-or gate in the domino multiplexer circuit. This clock signal synchronizes the input of the numbers to be added together and the addition operation in the domino multiplexer circuit.

Abstract: In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

Abstract: A first pull-up transistor has a gate coupled to a clock signal line and a drain coupled to both a first pull-down transistor and a voltage clamp. A second pull-up transistor has a gate that is also coupled to the clock signal line and a drain coupled to both a second pull-down transistor and a voltage clamp. A shared pull-down transistor has a gate that is also coupled to the clock signal line and a drain coupled to both the first and second pull-down transistors. This circuit may be found useful in clock buffering applications.

Abstract: A clock buffer includes a clocked pull-up transistor and a clocked pull-down transistor. The clocked pull-up transistor has a drain coupled to an output line and a gate coupled to a clock signal line. The clocked pull-down transistor includes a drain coupled to the output line, a gate coupled to the clock signal line, and having a width Y. The buffer further includes a first pull-down transistor having a drain coupled to a source of the clocked pull-down transistor, a gate coupled to a first input signal line, and having a width that is at least 10% greater than Y. This clock buffer provides reduced power consumption in comparison to a more conventional clock buffer.

Abstract: A circuit includes first and second pull-up transistors having first and second drains, respectively, each coupled to separate voltage clamps. The gates of each of the two pull-up transistors are coupled to a clock signal line. The circuit further includes a shared pull-down transistor, the gate of which is coupled to the clock signal line. The drain of the shared pull-down transistor is coupled to the first drain via at least one pull-down transistor in series with the shared pull-down transistor. The drain of the shared pull-down transistor is also coupled to the second drain via at least one pull-down transistor in series with the shared pull-down transistor. This circuit may be found useful in multiplexing applications.

Abstract: A broken stack domino priority encoder to provide a set of voltages to uniquely identify the position of a leading one or leading zero in a binary word, the domino priority encoder comprising a by-pass stack of nMOSFETs and a broken stack of nMOSFETs to discharge various nodes. The stack depth of nMOSFETs between each node and ground is minimized in order to maximize switching speed of the priority encoder.

Abstract: A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.

Abstract: An adder circuit to generate carry-outs and a method implemented by the adder circuit. First and second groups of consecutive group generate terms are calculated. The first group of group generate terms are combined to calculate a first result at a first logic level, and the second group of group generate terms are combined to calculate a second result at the same logic level. The first and second results are then combined to calculate a carry-out at a second logic level.

Abstract: A method and apparatus for providing a high speed tristate buffer. The buffer includes a p-channel pull-up transistor and a transfer gate. The source of the transistor is coupled to a voltage supply. The drain of the transistor is coupled to the buffer output. The gate of the transfer gate is coupled to a first clock source. The input to the transfer gate is a second clock source, and the output of the transfer gate is coupled to the gate of the p-channel transistor.