Abstract: Technology for operating word line switch transistors in a memory system. A memory system provides for separate control of the voltage to the gates of the word line switch transistors and a voltage to a well in which the word line switch transistors reside. This allows for a negative voltage to be applied to the gates and/or the well. However, if desired, a non-negative voltage (e.g., 0V) may be applied to the gates or the well.

Abstract: A coated article includes a substrate with a first surface and a second surface and a functional coating applied over the first surface or the second surface. The functional coating includes a blocking layer over at least a portion of the substrate; a metallic layer over at least a portion of the blocking layer; and a top layer over at least a portion of the metallic layer. The coated article has an optical color shift, as measured by ?Ecmc, of no more than 4.5 after tempering.

Abstract: A computer-implemented method including: collecting, by a computing device, specification documentation of a product and drift data of the product during a product lifecycle; analyzing, by the computing device, the specification documentation and the drift data of the product to identify anomalies between the specification documentation and the drift data of the product during different stages of the product lifecycle; computing, by the computing device, a score of each of the identified anomalies; recommending, by the computing device, solutions to fix selected anomalies based on their score and by using content-based recommendations; and displaying the recommended solutions to an end-user in a dashboard.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes word line switches coupled to word lines connected to memory cells. The word line switches are each configured to retain a switch threshold voltage and selectively connect the word lines to a common driver for supplying voltages thereto during a memory operation. A control means is configured to apply predetermined select block switch voltages to a first set of the word line switches connected to the word lines of a selected block. The predetermined select block switch voltages are based on the memory operation performed. The control means apply a predetermined unselect block switch voltage to a second set of the word line switches connected to the word lines of an unselected block. The predetermined unselect block switch voltage is selected to lower the switch threshold voltage of the word line switches of the second set.

Abstract: Embodiments disclosed herein are directed to a memory device, comprising a substrate including a word line switch well region; a non-volatile memory array including a plurality of memory strings of non-volatile storage elements arranged into rows and columns over the word line switch well region; a plurality of word lines, each word line is coupled to one or more rows of non-volatile storage elements; and control circuitry in communication with the non-volatile memory array. The control circuitry is configured to apply a negative voltage to the word line switch well region.

Abstract: A memory device includes a plurality of memory blocks including respective word lines; and a word line driver circuit including word line driver transistors. In one embodiment, the word line driver transistors are located in laterally offset rows. In another embodiment, at least one of a spacing between laterally adjacent word line driver transistors or a length of their source or drain region differs dependent on whether the transistors are connected to words lines in the same memory block or in different memory blocks.

Abstract: A coated article includes: a substrate; a first dielectric layer over at least a portion of the substrate; a first metallic layer over at least a portion of the first dielectric layer; a first primer layer over at least a portion of the first metallic layer; and a second dielectric layer over at least a portion of the first primer layer; where the first primer layer is selected from the group consisting of zinc, aluminum-doped silver, aluminum zinc, vanadium zinc, tungsten tantalum, titanium niobium, zirconium niobium, tungsten niobium, aluminum niobium, aluminum titanium, tungsten titanium, tantalum titanium, zinc titanium, zinc tin, indium zinc, silver zinc, gallium zinc, indium tin, mixtures thereof, combinations thereof, and alloys thereof.

Abstract: Technology for operating word line switch transistors in a memory system. A memory system provides for separate control of the voltage to the gates of the word line switch transistors and a voltage to a well in which the word line switch transistors reside. This allows for a negative voltage to be applied to the gates and/or the well. However, if desired, a non-negative voltage (e.g., 0V) may be applied to the gates or the well.

Abstract: A coated article includes: a substrate; a first dielectric layer over at least a portion of the substrate; a first metallic layer over at least a portion of the first dielectric layer; a first primer layer over at least a portion of the first metallic layer; and a second dielectric layer over at least a portion of the first primer layer; where the first primer layer is selected from the group consisting of zinc, aluminum-doped silver, aluminum zinc, vanadium zinc, tungsten tantalum, titanium niobium, zirconium niobium, tungsten niobium, aluminum niobium, aluminum titanium, tungsten titanium, tantalum titanium, zinc titanium, zinc tin, indium zinc, silver zinc, gallium zinc, indium tin, mixtures thereof, combinations thereof, and alloys thereof.

Abstract: The invention is directed to protective layers that protect functional layers applied over a substrate. The protective layer has a first protective film over at least a portion of the functional layer. The first protective film is titania, alumina, zinc oxide, tin oxide, zirconia, silica, or mixtures thereof. A second protective film over at least a portion of the first protective film. The second protective film contains titania and alumina and is an outermost film.

Abstract: A memory apparatus and method of operation are provided. The apparatus includes word line switches coupled to word lines connected to memory cells. The word line switches are each configured to retain a switch threshold voltage and selectively connect the word lines to a common driver for supplying voltages thereto during a memory operation. A control means is configured to apply predetermined select block switch voltages to a first set of the word line switches connected to the word lines of a selected block. The predetermined select block switch voltages are based on the memory operation performed. The control means apply a predetermined unselect block switch voltage to a second set of the word line switches connected to the word lines of an unselected block. The predetermined unselect block switch voltage is selected to lower the switch threshold voltage of the word line switches of the second set.

Abstract: A semiconductor structure includes a memory die and a logic die. The memory die includes a three-dimensional memory device that contains an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, and memory opening fill structures located in the two-dimensional array of memory openings, where each of the memory opening fill structures includes a respective vertical semiconductor channel, a respective drain region, and a vertical stack of memory elements located at levels of the electrically conductive layers, memory-side bonding pads, and a first peripheral circuit including first thin film transistors located between the three-dimensional memory device and the memory-side bonding pads. The logic die includes a logic-side substrate, logic-side bonding pads bonded to the memory-side bonding pads, and a second peripheral circuit located between the logic-side substrate and the logic-side bonding pads.

Abstract: A semiconductor structure includes a logic die containing a word line switching circuit containing a fin field effect transistor having at least one semiconductor fin, and a planar field effect transistor, and a memory die containing a three-dimensional memory device bonded to the logic die.

Abstract: A coated article includes a substrate, a functional layer over at least a portion of the substrate, and a protective coating over at least a portion of the functional layer, wherein an uppermost layer of the functional layer is a metal oxide layer, and wherein the protective coating comprises a metal nitride layer and a metal oxynitride layer that is disposed between and in contact with at least part of the metal nitride layer and the metal oxide layer of the functional layer.

Abstract: Methods of processing coated articles, such as transparencies, are provided comprising flash annealing one or more layers of the coated article. The one or more layers may be reflective metallic layers, such as silver layers, or comprise a transparent conductive oxide, such as indium tin oxide, or a semiconductor.

Abstract: A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.

Abstract: The present invention is directed to coated articles. A substrate is coated with an underlayer having at a first underlayer film made of a first high refractive index material. A transparent conductive oxide layer over at least a portion of the underlayer. An embedded film is embedded within the transparent conductive oxide layer wherein the embedded film comprises a second high refractive index material.

Abstract: A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.

Abstract: A non-volatile memory includes a plurality of word lines connected to non-volatile memory cells, a plurality of driver lines configured to carry one or more word line voltages, and a plurality of word line switches that selectively connect the driver lines to the word lines. To more efficiently utilize space on the die, the word line switches are arranged in a plurality of three dimensional stacks such that each stack of the plurality of stacks comprises multiple word line switches vertically stacked.

Abstract: The present invention is directed to coated articles. A substrate is coated with an underlayer having at a first underlayer film made of a first high refractive index material. A transparent conductive oxide layer over at least a portion of the underlayer. An embedded film is embedded within the transparent conductive oxide layer wherein the embedded film comprises a second high refractive index material.