Abstract: A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.

Abstract: An amplifier overload power limit circuit, system, and a method thereof comprising a monitoring of a current gain of a BJT based on a current detector and limiting power to the BJT based on the monitored current gain to prevent the BJT from driven into a saturation mode and the amplifier overdrive.

Abstract: A system includes an instrumentation amplifier (INA) including a first transistor coupled to a first input node, and a second transistor coupled to a second input node. The INA also includes a resistor coupled between the first transistor and the second transistor. The INA includes a gain resistor network coupled to the resistor and to the first and second transistors, where the gain resistor network includes two or more gain resistors. The system also includes a voltage to current converter, where the voltage to current converter is coupled to the resistor and the gain resistor network.

Abstract: An amplifier overload power limit circuit, system, and a method thereof comprising a monitoring of a current gain of a BJT based on a current detector and limiting power to the BJT based on the monitored current gain to prevent the BJT from driven into a saturation mode and the amplifier overdrive.

Abstract: An amplifier overload power limit circuit, system, and a method thereof comprising a monitoring of a current gain of a BJT based on a current detector and limiting power to the BJT based on the monitored current gain to prevent the BJT from driven into a saturation mode and the amplifier overdrive.

Abstract: An amplifier overload power limit circuit, system, and a method thereof comprising a monitoring of a current gain of a BJT based on a current detector and limiting power to the BJT based on the monitored current gain to prevent the BJT from driven into a saturation mode and the amplifier overdrive.

Abstract: An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.

Abstract: An input stage of an operational amplifier receives first and second input voltages. An output slew detection circuit decreases a first current responsive to slewing of an output of the operational amplifier and increases the first current responsive to no slewing. A slew boost and differential input voltage detection generates a second current at a first level when the first and second input voltages are approximately equal and to generate the second current at a second level, smaller than the first level, responsive to the first and second input voltages not being approximately equal. A voltage on a capacitor increases responsive to the first current from the output slew detection circuit increasing and responsive to the second current being at the second level. A current mirror is activated responsive to the voltage on the capacitor exceeding a second threshold. The current mirror decreases a third current of the input stage.

Abstract: Automated degaussing methods and apparatus are presented for degaussing a magnetic core in close loop fashion, in which a plurality of pulses are applied to a compensation coil magnetically coupled with the core with duration or energy being decreased in succeeding pulse cycles according to a discrete feedback algorithm, and with individual pulse polarities being set according to core magnetization polarity measured subsequent to an immediately preceding pulse.

Abstract: Automated degaussing methods and apparatus are presented for degaussing a magnetic core in close loop fashion, in which a plurality of pulses are applied to a compensation coil magnetically coupled with the core with duration or energy being decreased in succeeding pulse cycles according to a discrete feedback algorithm, and with individual pulse polarities being set according to core magnetization polarity measured subsequent to an immediately preceding pulse.

Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.

Abstract: A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin?) input signals, respectively. A pass transistor (P3) is coupled between first electrodes of the first and second input transistors. First (N1) and second (N2) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit (22) selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V19) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q0) when it is turned off in response to a large difference between the first and second input signals.

Abstract: An output stage (1-2) includes a gain circuit (Q1,Q2) for driving a base of a main transistor (Q3) having a collector coupled to an output (18) in response to an input signal V11) which also controls a base of an auxiliary transistor (Q7) having a collector coupled to the output. A clamping transistor (Q6) has a control electrode coupled to the base of the auxiliary transistor, a first electrode coupled to the output, and a second electrode coupled to provide feedback from the output via the gain circuit to the base of the main transistor and to provide feedback from the output to the base of the auxiliary transistor. When the auxiliary transistor goes into deep saturation it causes the clamping transistor to provide negative feedback from the output to the main output stage so as to prevent the main transistor from going into deep saturation.

Abstract: A differential input circuit (1-1) includes first (Q0) and second (Q1) input transistors having control electrodes coupled to first (Vin+) and second (Vin?) input signals, respectively. A pass transistor (P3) is coupled between first electrodes of the first and second input transistors. First (N1) and second (N2) level shift transistors have control electrodes coupled to the first and second input signals, respectively. A voltage selector circuit (22) selects a voltage on a first electrode of one of the first and second level shift transistors according to which is at a higher voltage, and produces a corresponding control voltage (V19) on a control electrode of the pass transistor so as to limit a voltage difference between the first electrode and the control electrode of the first input transistor (Q0) when it is turned off in response to a large difference between the first and second input signals.