Patents by Inventor Sudarshan V

Sudarshan V has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12238568
    Abstract: A virtual Radio Access Network (vRAN) system (300) for provisioning a virtual Radio Access Network (RAN) that is portable across one or more RAN hardware platforms is provided. The virtual Radio Access Network (vRAN) system (300) includes a waveform development kit (WDK) (302), and a waveform execution environment (304). The waveform development kit (302) defines at least one portable Radio Access Network (RAN) application into a form that is instantiated on a RAN hardware (326). The waveform execution environment (304) (i) monitors real-time schedulable resources in real-time, and (ii) collects one or more statistics and monitors the one or more statistics for network automation. The waveform execution environment (304) includes a RAN hypervisor (314) that virtualizes at least one attribute of a spectral resource required to provision the RAN that is portable across at least one hardware platform of the one or more RAN hardware platforms in the RAN hardware.
    Type: Grant
    Filed: May 16, 2021
    Date of Patent: February 25, 2025
    Assignee: TEJAS NETWORKS LIMITED
    Inventors: Parag Naik, Anindya Saha, Makarand Kulkami, Hemant Mallapur, Susmit Kumar Datta, Sandeep Pendharkar, Venugopal Kolathur, Sudarshan V
  • Publication number: 20230057887
    Abstract: A virtual Radio Access Network (vRAN) system (300) for provisioning a virtual Radio Access Network (RAN) that is portable across one or more RAN hardware platforms is provided. The virtual Radio Access Network (vRAN) system (300) includes a waveform development kit (WDK) (302), and a waveform execution environment (304). The waveform development kit (302) defines at least one portable Radio Access Network (RAN) application into a form that is instantiated on a RAN hardware (326). The waveform execution environment (304) (i) monitors real-time schedulable resources in real-time, and (ii) collects one or more statistics and monitors the one or more statistics for network automation. The waveform execution environment (304) includes a RAN hypervisor (314) that virtualizes at least one attribute of a spectral resource required to provision the RAN that is portable across at least one hardware platform of the one or more RAN hardware platforms in the RAN hardware.
    Type: Application
    Filed: May 16, 2021
    Publication date: February 23, 2023
    Inventors: Parag Naik, Saha Anindya, Makarand Kulkami, Hernant Mallapur, Susmit Kumar Datta, Sandeep Pendharkar, Venugopal Kolathur, Sudarshan V
  • Publication number: 20110225120
    Abstract: A system and method for maintaining a database with a plurality of replicas that are geographically distributed. A plurality of tables are stored in a first replica, each table including a plurality of records. The system identifying if the record is a stub and requesting a lease from a second replica designated as master for the record if the record is a stub. The system receiving a copy of the record from the second replica and storing data fields of the record in the first replica after receiving the lease.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: Yahoo! Inc.
    Inventors: Brian F. Cooper, Sudarshan V. Kadambi
  • Publication number: 20110225121
    Abstract: A method and system for maintaining a database with a plurality of replicas that are geographically distributed. A plurality of tables are stored in the database, each table includes a plurality of records. The location where each record is stored being controlled based on a constraint property included in the record.
    Type: Application
    Filed: March 11, 2010
    Publication date: September 15, 2011
    Applicant: Yahoo! Inc.
    Inventors: Brian F. Cooper, Sudarshan V. Kadambi
  • Patent number: 7719109
    Abstract: A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: May 18, 2010
    Assignee: Intel Corporation
    Inventors: Mitul Modi, Sudarshan V. Rangaraj, Shankar Ganapathysubramanian, Richard J. Harries, Sankara J. Subramanian
  • Patent number: 7585693
    Abstract: Method of forming a microelectronic package using control of die and substrate differential expansions. The method includes: providing a die-substrate combination including a substrate, a die disposed on the substrate, and plurality of solder paste disposed between the die and the substrate; reflowing the solder paste by exposing the die-substrate combination to temperatures changes including heating the die-substrate combination to liquefy the solder paste, and cooling down the die-substrate combination until the solder paste has solidified to form solder joints to yield the package; and controlling an expansion of the die and the substrate at least during cooling down to mitigate a relative difference in volumetric strain between the die and the substrate. Controlling may comprise exposing the die-substrate combination to pressure changes at least during cooling down.
    Type: Grant
    Filed: March 31, 2006
    Date of Patent: September 8, 2009
    Assignee: Intel Corporation
    Inventors: Kristopher J. Frutschy, Sudarshan V. Rangaraj, Kevin B. George
  • Publication number: 20090065931
    Abstract: Disclosed is a packaged integrated circuit and a method of forming thereof. The packaged integrated circuit includes a substrate, a plurality of solder bumps, a semiconductor die and a plurality of copper bumps. The plurality of solder bumps are configured on the substrate. Each of the plurality of solder bumps has a height of about 40 micrometers (?m) to about 65 ?m. Further, the plurality of copper bumps are configured on the semiconductor die. Each of the plurality of copper bumps has a height of about 10 ?m to about 25 ?m. The semiconductor die is disposed above the substrate such that the plurality of copper bumps are coupled to the plurality of solder bumps, which in turn, couples the semiconductor die to the substrate.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Applicant: INTEL CORPORATION
    Inventors: Sudarshan V. Rangaraj, Sanka Ganesan, Dongming He, Richard J. Harries, Sairam Agraharam
  • Publication number: 20080096310
    Abstract: A linear coefficient of thermal expansion (CTE) mismatch between two materials, such as between a microelectronic die and a mounting substrate, may induce stress at the interface of the materials. The temperature changes present during the process of attaching a die to a mounting substrate can cause cracking and failure in the electrical connections used to connect the die and mounting substrate. A material with a CTE approximately matching the die CTE is introduced in the mounting substrate to reduce the stress and cracking at the electrical connections between the die and mounting substrate. Additionally, this material may comprise thin film capacitors useful for decoupling power supplies.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 24, 2008
    Inventors: Mitul Modi, Sudarshan V. Rangaraj, Shankar Ganapathysubramanian, Richard J. Harries, Sankara J. Subramanian
  • Publication number: 20080001282
    Abstract: A microelectronic assembly is provided, comprising at least a first microelectronic die carrying a microelectronic circuit, at least a first periphery seal attached to an edge of a surface of the microelectronic die, at least a first solder thermal interface material attached to a central region of the surface of the microelectronic die, the solder thermal interface material having a higher thermal conductivity than the periphery seal, and a thermally conductive member attached to the periphery seal and the solder thermal interface material on a side thereof opposing the microelectronic die.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventors: Mitul Modi, Sudarshan V. Rangaraj, Shankar Ganapathysubramanian, Richard J. Harries, Sankara J. Subramanian
  • Patent number: 7288472
    Abstract: Embodiments of a method for attaching a die to a substrate using a flame or other heat source are disclosed. The flame may be produced by combustible gas. Also disclosed are embodiments of a system for performing die attach using a flame. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 21, 2004
    Date of Patent: October 30, 2007
    Assignee: Intel Corporation
    Inventors: Kris J. Frutschy, Sudarshan V. Rangaraj, Tom M. Lappin