Patents by Inventor Sudarshanram Shetty

Sudarshanram Shetty has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230111571
    Abstract: Embodiments described herein are generally directed facilitating out-of-order execution of GPU texture sampler operations. An embodiment of a method includes a texture sampler of a GPU maintaining (i) a latency queue operable to store information regarding a set of transactions associated with each of multiple texture sampler operations and (ii) multiple virtual channel (VC) queues each operable to store information regarding transactions for a respective single texture sampler operation at a time. Out-of-order processing of the texture sampler operations is facilitated by making use of the latency queue and the VC queues. For example, during a transaction processing interval, the availability of data in a cache for the transactions associated with each of the VC queues may be determined. A VC queue may be selected based on the determined availability of data. A transaction associated with a head of the selected VC queue may then be processed.
    Type: Application
    Filed: September 24, 2021
    Publication date: April 13, 2023
    Applicant: Intel Corporation
    Inventors: Carlos Nava Rodriguez, Benjamin Pletcher, Yoav Harel, Bret Martin, Sudarshanram Shetty
  • Patent number: 11386013
    Abstract: An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: July 12, 2022
    Assignee: Intel Corporation
    Inventors: Sudarshanram Shetty, Ping Hang Cheung, Aravindh Anantaraman, Travis Schluessler
  • Publication number: 20210390058
    Abstract: An apparatus to facilitate dynamic cache control is disclosed. The apparatus includes one or more processors to profile execution characteristics of a graphics workload at a processing resource to generate profile data indicating a quantity of cache hits that occur at a cache memory and apply one or more cache settings to the cache memory based on the profile data.
    Type: Application
    Filed: June 16, 2020
    Publication date: December 16, 2021
    Applicant: Intel Corporation
    Inventors: Sudarshanram Shetty, Ping Hang Cheung, Aravindh Anantaraman, Travis Schluessler