Patents by Inventor Sudeep Bhoja

Sudeep Bhoja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240063940
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Application
    Filed: October 26, 2023
    Publication date: February 22, 2024
    Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
  • Publication number: 20240037379
    Abstract: A server system with AI accelerator apparatuses using in-memory compute chiplet devices. The system includes a plurality of multiprocessors each having at least a first server central processing unit (CPU) and a second server CPU, both of which are coupled to a plurality of switch devices. Each switch device is coupled to a plurality of AI accelerator apparatuses. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a CPU, and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions.
    Type: Application
    Filed: October 13, 2023
    Publication date: February 1, 2024
    Inventors: Jayaprakash BALACHANDRAN, Akhil ARUNKUMAR, Aayush ANKIT, Nithesh Kurella, Sudeep Bhoja
  • Patent number: 11888613
    Abstract: An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: January 30, 2024
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Benjamin Smith, Jamal Riani, Arash Farhoodfar, Sudeep Bhoja
  • Patent number: 11886359
    Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.
    Type: Grant
    Filed: October 17, 2022
    Date of Patent: January 30, 2024
    Assignee: d-MATRIX CORPORATION
    Inventors: Sudeep Bhoja, Siddharth Sheth
  • Patent number: 11855702
    Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: December 26, 2023
    Assignee: MARVELL ASIA PTE LTD
    Inventors: Benjamin P. Smith, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
  • Patent number: 11847072
    Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: December 19, 2023
    Assignee: d-MATRIX CORPORATION
    Inventors: Sudeep Bhoja, Siddharth Sheth
  • Patent number: 11804925
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: October 31, 2023
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
  • Publication number: 20230168899
    Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications, including generative AI. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions.
    Type: Application
    Filed: November 23, 2022
    Publication date: June 1, 2023
    Inventors: Sudeep BHOJA, Siddharth SHETH
  • Publication number: 20230169023
    Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.
    Type: Application
    Filed: October 17, 2022
    Publication date: June 1, 2023
    Inventors: Sudeep BHOJA, Siddharth Sheith
  • Publication number: 20230169021
    Abstract: An AI accelerator apparatus using in-memory compute chiplet devices. The apparatus includes one or more chiplets, each of which includes a plurality of tiles. Each tile includes a plurality of slices, a central processing unit (CPU), and a hardware dispatch device. Each slice can include a digital in-memory compute (DIMC) device configured to perform high throughput computations. In particular, the DIMC device can be configured to accelerate the computations of attention functions for transformer-based models (a.k.a. transformers) applied to machine learning applications. A single input multiple data (SIMD) device configured to further process the DIMC output and compute softmax functions for the attention functions. The chiplet can also include die-to-die (D2D) interconnects, a peripheral component interconnect express (PCIe) bus, a dynamic random access memory (DRAM) interface, and a global CPU interface to facilitate communication between the chiplets, memory and a server or host system.
    Type: Application
    Filed: November 30, 2021
    Publication date: June 1, 2023
    Inventors: Sudeep BHOJA, Siddharth SHETH
  • Patent number: 11575396
    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: February 7, 2023
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Jamal Riani, Farshid Rafiee Rad, Benjamin P. Smith, Yu Liao, Sudeep Bhoja
  • Patent number: 11451300
    Abstract: The present invention is directed to data communication system and methods. More specifically, various embodiments of the present invention provide a communication interface that is configured to transfer data at high bandwidth using nDSQ format(s) over optical communication networks. In certain embodiments, the communication interface is used by various devices, such as spine switches and leaf switches, within a spine-leaf network architecture, which allows large amount of data to be shared among servers.
    Type: Grant
    Filed: January 28, 2021
    Date of Patent: September 20, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Sudeep Bhoja
  • Publication number: 20220201225
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Application
    Filed: March 14, 2022
    Publication date: June 23, 2022
    Inventors: Jamal RIANI, Benjamin SMITH, Volodymyr SHVYDUN, Sudeep BHOJA, Arash FARHOODFAR
  • Publication number: 20220173814
    Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
    Type: Application
    Filed: February 17, 2022
    Publication date: June 2, 2022
    Inventors: Benjamin P. SMITH, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
  • Publication number: 20220158759
    Abstract: An optical transmitter includes a first encoder, a first interleaver, a second encoder, a mapper, a second interleaver, and a frame generator. The first encoder is configured to encode data using a staircase code to generate first codewords. The first interleaver is configured to interleave the first codewords using convolutional interleaving to spread a transmission order of the first codewords. The second encoder is configured to encode the interleaved first codewords using a second code to generate second codewords. The mapper is configured to map the second codewords to transmit symbols. The second interleaver is configured to interleave the transmit symbols to distribute the transmit symbols between pilot symbols. The frame generator is configured to generate a transmit frame including the interleaved transmit symbols and the pilot symbols.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Inventors: Benjamin Smith, Jamal Riani, Arash Farhoodfar, Sudeep Bhoja
  • Patent number: 11277224
    Abstract: A method for data transmission includes receiving a data stream from a host device, the data stream as received from the host device including encoded data, separating the encoded data in the data stream into first data blocks and second data blocks, and generating a first forward error correction (FEC) block. The first FEC block includes a first parity section and a first data section, the first parity section includes a first parity bit corresponding to the first data blocks and a second parity bit corresponding to the second data blocks, and the first data section includes the first data blocks and the second data blocks. The method further includes transmitting the first FEC block.
    Type: Grant
    Filed: July 14, 2020
    Date of Patent: March 15, 2022
    Assignee: Marvell Asia Pte Ltd.
    Inventors: Jamal Riani, Benjamin Smith, Volodymyr Shvydun, Sudeep Bhoja, Arash Farhoodfar
  • Patent number: 11265011
    Abstract: Embodiments relate to the emulation of the effect of Forward Error Correction (FEC) codes, e.g., GF10 Reed Solomon (RS) FEC codes, on the bit error ratio (BER) of received Pseudo-Random Binary Sequences (PRBS) patterns. In particular, embodiments group errors into RS-FEC symbols and codewords in order to determine if the errors are correctable. By emulating the error correction capabilities of FEC codes in order to determine which errors are correctable by the code, embodiments afford a more accurate representation of the post-FEC BER of RS FEC codes from links carrying PRBS patterns. This FEC code emulation provides error correction statistics, for stand-alone use or for error correction in connection with Bit Error Rate Testers (BERTs).
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: March 1, 2022
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Andre Szczepanek, Arash Farhoodfar, Sudeep Bhoja, Sean Batty, Shaun Lytollis
  • Patent number: 11258518
    Abstract: A circuit and method for mitigating multi-path interference in direct detection optical systems is provided. Samples of an optical signal having a pulse amplitude modulated (PAM) E-field are processed by generating a PAM level for each sample. For each sample, the sample is subtracted from the respective PAM level to generate a corresponding error sample. The error samples are lowpass filtered to produce estimates of multi-path interference (MPI). For each sample, one of the estimates of MPI is combined with the sample to produce an interference-mitigated sample.
    Type: Grant
    Filed: November 18, 2020
    Date of Patent: February 22, 2022
    Assignee: MARVELL ASIA PTE LTD.
    Inventors: Benjamin P. Smith, Jamal Riani, Sudeep Bhoja, Arash Farhoodfar, Vipul Bhatt
  • Patent number: 11245493
    Abstract: The present invention relates to data communication systems and methods thereof. More specifically, embodiments of the present invention provide a data transmission method. Data are encoded with staircase encoder, and staircase coded blocks are first interleaved then combined into outer code frames. Code frames additionally include sync words and padding bits. A second interleaving is applied to the bits of the code frames, and Hamming encoding is performed on the output of the second interleaver. Hamming codewords are Gray-mapped to dual-polarized quadrature-amplitude-modulation (DP-QAM) symbols, and a third interleaving of the symbols from a set of successive Hamming codewords is performed. Pilot symbols are inserted periodically into the stream of DP-QAM symbols. There are other embodiments as well.
    Type: Grant
    Filed: December 1, 2020
    Date of Patent: February 8, 2022
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: Benjamin P. Smith, Jamal Riani, Arash Farhoodfar, Sudeep Bhoja
  • Publication number: 20210306009
    Abstract: The present invention is directed to data communication. More specifically, an embodiment of the present invention provides an error correction system. Input data signals are processed by a feedforward equalization module and a decision feedback back equalization module. Decisions generated by the decision feedback equalization module are processed by an error detection module, which determines error events associated with the decisions. The error detection module implements a reduced state trellis path. There are other embodiments as well.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Inventors: Jamal RIANI, Farshid RAD, Benjamin P. SMITH, Yu LIAO, Sudeep BHOJA