Abstract: The present disclosure relates to methods and devices for video or frame processing including an apparatus, e.g., a video or frame processor. In some aspects, the apparatus may receive a video stream including a plurality of frames, each of the plurality of frames including luminance information. The apparatus may also perform a histogram analysis on the luminance information for each of the plurality of frames. Additionally, the apparatus may determine whether a difference between the luminance information for each of the plurality of frames and a current luminance distribution is greater than a perceptual threshold. The apparatus may also calculate an updated tone mapping configuration based on the luminance information for a frame when the difference between the luminance information for the frame and the current luminance distribution is greater than the perceptual threshold.

Abstract: The present disclosure relates to methods and devices for video or frame processing including an apparatus, e.g., a video or frame processor. In some aspects, the apparatus may receive a video stream including a plurality of frames, each of the plurality of frames including luminance information. The apparatus may also perform a histogram analysis on the luminance information for each of the plurality of frames. Additionally, the apparatus may determine whether a difference between the luminance information for each of the plurality of frames and a current luminance distribution is greater than a perceptual threshold. The apparatus may also calculate an updated tone mapping configuration based on the luminance information for a frame when the difference between the luminance information for the frame and the current luminance distribution is greater than the perceptual threshold.

Abstract: In some aspects, the present disclosure provides a method for generating a frame. The method includes receiving a first fence indicating that a first frame stored in a display processor unit (DPU) buffer has been consumed by a hardware component. The method also includes in response to receiving the first fence, fetching a plurality of layers from an application buffer, the plurality of layers corresponding to a second frame. The method also includes determining to use both a DPU and a graphics processing unit (GPU) to process the plurality of layers for composition of the second frame. The method also includes fetching the first fence from the DPU buffer and generating a second fence.

Abstract: Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.

Abstract: Various aspects include computing device methods for managed virtual machine memory access. Various aspects may include receiving a memory access request from a managed virtual machine having a virtual address, retrieving a first physical address for a stage 2 page table for a managing virtual machine, in which the stage 2 page table is stored in a physical memory space allocated to a hypervisor, retrieving a second physical address from an entry of the stage 2 page table for a stage 1 page table for a process executed by the managed virtual machine, in which the second physical address is for a physical memory space allocated to the managing virtual machine and the stage 1 page table is stored in that physical memory space, and retrieving a first intermediate physical address from an entry of the stage 1 page table for a translation of the virtual address.

Abstract: Techniques are described in which a video decoding mode is used to determine which regions of a picture need to be composed. If a region of a current picture is decoded in skip mode with the reference picture of the skip mode being a previous picture that is displayed immediately prior to the current picture, then pixel values for that region may not need to be retrieved from system memory.

Abstract: A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.

Abstract: Techniques are described in which a video decoding mode is used to determine which regions of a picture need to be composed. If a region of a current picture is decoded in skip mode with the reference picture of the skip mode being a previous picture that is displayed immediately prior to the current picture, then pixel values for that region may not need to be retrieved from system memory.

Abstract: A device and method of decoding video data that includes decoding the video data to generate decoded video data of a current frame of the video data, and extracting an updated regions message from the decoded video data and determining updated region location information of the current frame based on the updated regions message. An updated region of the current frame is identified based on the updated region location information, the updated region being less than a total size of the current frame, and both the identified updated region and decoded video data of the current frame that has not been updated are transmitted for display of the current frame of the video data.

Abstract: Systems, methods, and computer programs are disclosed for controlling memory frequency. One method comprises a first memory client generating a compressed data buffer and compression statistics related to the compressed data buffer. The compressed data buffer and the compression statistics are stored in a memory device. Based on the stored compression statistics, a frequency or voltage setting of the memory device is adjusted for enabling a second memory client to read the compressed data buffer.

Abstract: A transparent format converter (TFC) may determine that a request by at least one processor for graphics data stored in graphics memory is indicative of a request for graphics data in a first data format. The TFC may retrieve the graphics data in a second data format from the graphics memory based at least in part on the request for the graphics data in the graphics memory. The TFC may convert the retrieved graphics data from the second data format to the first data format. The TFC may store the converted graphics data in the first data format into a memory that is accessible by the at least one processor.

Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by translating virtual memory addresses into physical addresses on a computing system having hybrid memory. In a first stage of memory translation, an operating system translates virtual addresses to intermediate physical addresses. In a second stage of memory translation, a chip or virtualization software translates the intermediate physical address to physical addresses based on the characteristics of the physical memory and the characteristics of the processes associated with the physical memory.

Abstract: Disclosed is a processor for processing data from a buffer memory. The processor, implemented in hardware, may allow writing of output data, processed based on input data from at least one secure location associated with a secure address range of the buffer memory, to one or more secure locations associated with the secure address range. Further, the processor may block writing of output data, processed based on input data from at least one secure location associated with the secure address range, to one or more insecure locations associated with an insecure address range of the buffer memory.

Abstract: The disclosure is directed to managing registration of a wireless communication device (WCD) operating in a wireless network. The WCD may support registration according to a signaling protocol, such as session initiation protocol (SIP). The WCD adjusts a registration timer based on network quality experienced by the WCD. When network quality is poor, for example, the WCD reduces the length of the registration timer. Reduced network quality may indicate that the WCD is at risk of losing network coverage. By reducing the length of the registration timer when network quality is degraded, stale registrations for out-of-coverage WCDs can be reduced. In particular, the shortened registration timer will expire more quickly, permitting the registration to be cleared more quickly. Consequently, the amount of call forwarding and other resources devoted to stale registrations can be reduced. If the WCD retains network coverage, it can maintain a registration by sending another registration request.

Abstract: A processor is utilized for processing data from a buffer memory. The processor, implemented in hardware, may allow writing of output data, processed based on input data from at least one secure location associate with a secure address range of the buffer memory, to one or more secure locations associated with the secure address range. Further, the processor may block writing of output data, processed based on input data from at least one secure location associated with the secure address range, to one or more insecure locations associated with an insecure address range of the buffer memory.

Abstract: A graphics processing unit (GPU) is configured to access a first memory unit according to one of an unsecure mode and a secure mode. The GPU may include a memory access controller configured to allow the GPU to read data from only an unsecure portion of the first memory unit when the GPU is in the unsecure mode, and configured to allow the GPU to write data only to a secure portion of the first memory unit when the GPU is in the secure mode.

Abstract: Generally, aspects of this disclosure are directed to copy protection techniques. Areas in memory may be secured to establish a secure memory area in the memory that is not accessible by unauthorized clients. A request to decode video content stored in the secure memory area may be received. If the video content to be decoded is stored in the secure memory area, a first MMU associated with the hardware decoder may enforce a rule that the video content is to be decoded into one or more output buffers in the secure memory area. A request to display the decoded video content stored in the secure memory area may be received. If the decoded video content is stored in the secure memory area, a second MMU associated with a hardware display processor may enforce a rule that a secure link be established between the hardware display processor and an output device.

Abstract: This disclosure proposes techniques for graphics processing. In one example, a graphics processing unit (GPU) is configured to access a first memory unit according to one of an unsecure mode and a secure mode. The GPU comprises a memory access controller configured to allow the GPU to read data from only an unsecure portion of the first memory unit when the GPU is in the unsecure mode, and configured to allow the GPU to write data only to a secure portion of the first memory unit when the GPU is in the secure mode.

Abstract: In the various aspects, virtualization techniques may be used to improve performance and reduce the amount of power consumed by translating virtual memory addresses into physical addresses on a computing system having hybrid memory. In a first stage of memory translation, an operating system translates virtual addresses to intermediate physical addresses. In a second stage of memory translation, a chip or virtualization software translates the intermediate physical address to physical addresses based on the characteristics of the physical memory and the characteristics of the processes associated with the physical memory.

Abstract: Systems, methods, and devices for processing video data are disclosed. Some examples include a content receiver including an unsecure processor and an unsecure memory coupled to the unsecure processor. The example includes content protection zone hardware including a secure memory and an input for receiving content. The input coupled to the content protection zone hardware, wherein the content protection zone hardware determines if the received content is secure or unsecure and directs secure content to the secure memory and unsecure content to the unsecure memory.