Abstract: Methods, systems, and computer readable media for utilizing an augmented neural network are disclosed. In one embodiment, the method includes utilizing a neural network (NN) pre-processor to convert generic coordinates associated with a dynamical system to canonical coordinates, concatenating a Hamiltonian neural network (HNN) to the NN pre-processor to create a generalized HNN, and training the generalized HNN to learn nonlinear dynamics present in the dynamical system from generic training data. The method also includes utilizing the trained generalized HNN to forecast the nonlinear dynamics, and quantifying chaotic behavior from the forecasted nonlinear dynamics to discover and map one or more transitions between orderly states and chaotic states exhibited by the dynamical system.

Abstract: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.

Abstract: A nanomechanical device, operating as a reprogrammable logic gate, and performing fundamental logic functions such as AND/OR and NAND/NOR. The logic function can be programmed (e.g., from AND to OR) dynamically, by adjusting the operating parameters of the resonator. The device can access one of two stable steady states, according to a specific logic function; this operation is mediated by the noise floor which can be directly adjusted, or dynamically tuned via an adjustment of the underlying nonlinearity of the resonator, i.e., it is not necessary to have direct control over the noise floor. The demonstration of this reprogrammable nanomechanical logic gate affords a path to the practical realization of a new generation of mechanical computers.

Abstract: A dynamical search engine for searching a database is also provided. The dynamical search engine includes an array of nonlinear dynamical elements. The nonlinear dynamical element information items in a manner that confines the state of each element on a fixed point and uniquely encodes the information items. The dynamical search engine also includes a controller for controlling electrical signals supplied to elements of the array in a predetermined sequence. One supplied signal increases a state value of each element of the array by a quantity defining a search key that corresponds to a searched-for information item. A subsequently supplied signal updates the state value of each element of the array by performing a nonlinear folding of each state value based on a predetermined pivot.

Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.

Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.

Abstract: A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.

Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.

Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.

Abstract: A dynamical search engine for searching a database is also provided. The dynamical search engine includes an array of nonlinear dynamical elements. The nonlinear dynamical element information items in a manner that confines the state of each element on a fixed point and uniquely encodes the information items. The dynamical search engine also includes a controller for controlling electrical signals supplied to elements of the array in a predetermined sequence. One supplied signal increases a state value of each element of the array by a quantity defining a search key that corresponds to a searched-for information item. A subsequently supplied signal updates the state value of each element of the array by performing a nonlinear folding of each state value based on a predetermined pivot.

Abstract: A logic gate is adapted to implement logical expressions. The logic gate includes at least one input that is adapted to receive an input signal and at least one control signal. At least one of the input signal and the control signal is a noise signal. At least one output is adapted to produce an output signal. A nonlinear updater operates as a dynamically configurable element and produces multiple different logic gates as selected by the control signal based at least in part on the noise signal. The nonlinear updater is electrically coupled to the input and is also electrically coupled to the output. The nonlinear updates is configured to apply a nonlinear function to the input signal in response to the control signal to produce the output signal representing a logical expression being implemented by one of the multiple different logic gates on the input signal.

Abstract: A logic gate implements logical expressions. A least one logic gate input receives at least one input logic gate signal and at least one control signal. At least one output for produces a logic gate output signal. A nonlinear updater operates as a dynamically configurable element to produce a plurality of different logic gates as selected by the control signal. The nonlinear updater includes a nonlinear updater output. The nonlinear updater is configured to apply a nonlinear function to the input logic gate signal to produce the nonlinear updater output signal representing a logical expression being implemented by one of the plurality of different logic gates on the input logic gate signal. A comparator includes a comparator input that is adapted to receive a reference threshold value for producing the logical gate output signal based on a comparison of the nonlinear output signal to the reference threshold value.

Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.

Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.

Abstract: A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.

Abstract: A logic gate array for implementing logical expressions is provided. The array includes a dynamically configurable logic gate having a chaotic updater for causing the logic gate to alternately operate as one of a several different logic gate types, the dynamically configurable logic gate alternating from operating as one logic gate type to a different logic gate type in response to one or more reference signals. The array also includes one or more additional logic gates.

Abstract: A dynamically configurable logic gate can include a controller configured to provide a first threshold reference signal; an adder configured to sum the first threshold reference signal and at least one input signal to generate a summed signal; a chaotic updater configured to apply a nonlinear function to the summed signal; and a subtractor configured to determine an output signal by taking a difference between a second threshold reference signal and the processed summed signal from the chaotic updater. The logic gate can operate as one of a plurality of different logic gates responsive to adjusting at least one of the threshold reference signals.