Patents by Inventor Sudha Sarma

Sudha Sarma has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5918242
    Abstract: A memory controller design includes at least one memory instruction decoder de-embedded from a memory instruction processor wherein the memory instruction processor receives operations and logical address information from a host processor. The memory instruction processor converts the operations into generic memory instructions and translates the logical addresses into physical addresses. The memory instruction decoder further converts the generic memory instructions into memory specific control signals and converts the physical addresses into actual memory specific addresses. This design permits the memory instruction processor to be designed and finalized before an actual memory type is selected for system use at which time the less complex memory instruction decoder can be designed.
    Type: Grant
    Filed: February 24, 1997
    Date of Patent: June 29, 1999
    Assignee: International Business Machines Corporation
    Inventors: Sudha Sarma, Adalberto Guillermo Yanes
  • Patent number: 5684978
    Abstract: For an synchronous dynamic access memory ("S-DRAM") system including a memory assembly with multiple memory units, data access commands are placed on a command bus at specific times to facilitate gapless data bus operation. After receipt of a first memory access request, a first memory access command is issued on the command bus to exchange a first data string having a first length with a first one of the memory units. Subsequently, receipt occurs of a second memory access request is to exchange a second data string, of a second length, with a second one of the memory units. A determination is made of an earliest possible time for placement of a second memory access command upon the command bus; this considers various factors, such as the first length, data bus availability, command bus availability, and any predetermined delay in placement of the first data string onto the data bus. Accordingly, the second memory access command is placed upon the command bus at the determined time.
    Type: Grant
    Filed: October 20, 1995
    Date of Patent: November 4, 1997
    Assignee: International Business Machines Corporation
    Inventors: Sudha Sarma, Adalberto Guillermo Yanes
  • Patent number: 5577236
    Abstract: A memory controller reads data from a memory bank of synchronous RAM during a small and variable data valid window, by compensating for delays in receiving the data caused by memory loading, chip and card manufacturing process variations, and the like. The memory controller includes a system clock driver to supply the memory bank with a clock reference signal. A sampling clock provides an assortment of sampling clock signals duplicative of the system clock signal, with various delays. A command driver initiates Read operations in the memory bank by relaying Read command signals to the memory bank. In response to the level of memory loading, such as the number of memory modules present in the memory bank, a clock selector directs a selected one of the sampling clock signals to a delay module, which replicates any delay the system clock driver may have.
    Type: Grant
    Filed: December 30, 1994
    Date of Patent: November 19, 1996
    Assignee: International Business Machines Corporation
    Inventors: Mark C. Johnson, Donald J. Lang, Sudha Sarma, Forrest L. Wade, Adalberto G. Yanes