Patents by Inventor SUDHA THIPPARTHI

SUDHA THIPPARTHI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Constrained on-the-fly interleaver address generator circuits, systems, and methods
    Patent number: 8913336
    Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: December 16, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Sivagnanam Parthasarathy, Shayan Srinivasa Garani, Sudha Thipparthi
  • CONSTRAINED ON-THE-FLY INTERLEAVER ADDRESS GENERATOR CIRCUITS, SYSTEMS, AND METHODS
    Publication number: 20140111882
    Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
    Type: Application
    Filed: January 2, 2014
    Publication date: April 24, 2014
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Sivagnanam PARTHASARATHY, Shayan Srinivasa GARANI, Sudha THIPPARTHI
  • Constrained on-the-fly interleaver address generator circuits, systems, and methods
    Patent number: 8625220
    Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: January 7, 2014
    Assignee: STMicroelectronics, Inc.
    Inventors: Sivagnanam Parthasarathy, Shayan Garani Srinivasa, Sudha Thipparthi
  • CONSTRAINED ON-THE-FLY INTERLEAVER ADDRESS GENERATOR CIRCUITS, SYSTEMS, AND METHODS
    Publication number: 20110080669
    Abstract: An interleave address generation circuit includes a plurality of linear feedback shift registers operable to generate addresses for permuting a data block in a first domain to a data block in a second domain on a subword basis. The interleave address generation circuit is operable to generate the lane addresses for each subword and the linear feedback registers configured to generate circulant addresses and sub-circulant address to map bits in each subword in the data block in the first domain to a corresponding subword in the second domain.
    Type: Application
    Filed: October 1, 2010
    Publication date: April 7, 2011
    Applicant: STMICROELECTRONICS, INC.
    Inventors: SIVAGNANAM PARTHASARATHY, SHAYAN GARANI SRINIVASA, SUDHA THIPPARTHI