Patents by Inventor Sudha Thiruvengadam
Sudha Thiruvengadam has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9891271Abstract: A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules.Type: GrantFiled: July 19, 2013Date of Patent: February 13, 2018Assignee: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, Joel Irby, Sudha Thiruvengadam, Carl Dietz
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Patent number: 9639488Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.Type: GrantFiled: June 20, 2014Date of Patent: May 2, 2017Assignee: Advanced Micro Devices, Inc.Inventors: Gregory Sadowski, Sudha Thiruvengadam, Arun Iyer
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Patent number: 9405357Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.Type: GrantFiled: April 1, 2013Date of Patent: August 2, 2016Assignee: Advanced Micro Devices, Inc.Inventors: Stephen V. Kosonocky, Christopher Spence Oliver, Sudha Thiruvengadam, Carson D. Henrion
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Publication number: 20150372802Abstract: Embodiments are described for a method of reducing power consumption in source synchronous bus systems by reducing signal transitions in the system. Instead of sending clock and data valid signals, only the start and end of valid data packets are marked by clock signal transitions, or only a number of clock pulses that corresponds to number of data words is sent, or only a number transitions on clock signals are sent. The clock signal transitions may comprise either clock pulses or exclusively rising edge or falling edge transitions of the clock signal.Type: ApplicationFiled: June 20, 2014Publication date: December 24, 2015Inventors: Gregory Sadowski, Sudha Thiruvengadam, Arun Iyer
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Patent number: 9143315Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.Type: GrantFiled: October 25, 2013Date of Patent: September 22, 2015Assignee: Advanced Micro Devices, Inc.Inventors: Mark Buckler, Sudha Thiruvengadam
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Publication number: 20150117582Abstract: Embodiments are described for a method and system of enabling updates from a clock controller to be sent directly to a predictive synchronizer to manage instant changes in frequency between transmit and receive clock domains, comprising receiving receive and transmit reference frequencies from a phase-locked loop circuit, receiving receive and transmit constant codes from a controller coupled to the phase-locked loop circuit, obtaining a time delay factor to accommodate phase detection between the transmit and receive clock domains, and calculating new detection interval and frequency information using the time delay factor, the reference frequencies, and the constant codes.Type: ApplicationFiled: October 25, 2013Publication date: April 30, 2015Applicant: ADVANCED MICRO DEVICES, INC.Inventors: Mark Buckler, SUDHA THIRUVENGADAM
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Publication number: 20150026407Abstract: As a processor enters selected low-power modes, a cache is flushed of data by writing data stored at the cache to other levels of a memory hierarchy. The flushing of the cache allows the size of the cache to be reduced without suffering an additional performance penalty of writing the data at the reduced cache locations to the memory hierarchy. Accordingly, when the cache exits the selected low-power modes, it is sized to a minimum size by setting the number of ways of the cache to a minimum number. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Edward J. McLellan, Sudha Thiruvengadam, Douglas R. Beard, Carl D. Dietz, Stephen V. Kosonocky
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Publication number: 20150022218Abstract: A power grid provides power to one or more modules of an integrated circuit device via a virtual power supply signal. A test module is configured to respond to assertion of a test signal so that, when the power grid is working properly and is not power gated, an output of the test module matches the virtual power supply. When the power grid is not working properly, the output of the test module is a fixed logic signal that does not vary based on the power gated state of the one or more modules.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Russell Schreiber, Joel Irby, Sudha Thiruvengadam, Carl Dietz
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Publication number: 20150026406Abstract: A size of a cache of a processing system is adjusted by ways, such that each set of the cache has the same number of ways. The cache is a set-associative cache, whereby each set includes a number of ways. In response to defined events at the processing system, a cache controller changes the number of ways of each set of the cache. For example, in response to a processor core indicating that it is entering a period of reduced activity, the cache controller can reduce the number of ways available in each set of the cache.Type: ApplicationFiled: July 19, 2013Publication date: January 22, 2015Applicant: Advanced Micro Devices, Inc.Inventors: Edward J. McLellan, Sudha Thiruvengadam, Douglas R. Beard, Carl D. Dietz, Stephen V. Kosonocky
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Publication number: 20140298068Abstract: An integrated circuit device includes a first module disposed within a first power domain, a second module disposed in a second power domain that is a sub-domain of the first power domain, first power gating logic, and second power gating logic. The first power gating logic generates a first virtual power supply for the first module. The second power gating logic is powered by the first virtual power supply for generating a second virtual power supply for the second power domain.Type: ApplicationFiled: April 1, 2013Publication date: October 2, 2014Applicant: Advanced Micro Devices, Inc.Inventors: Stephen V. Kosonocky, Christopher Spence Oliver, Sudha Thiruvengadam, Carson D. Henrion
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Publication number: 20090046519Abstract: A computer-implemented method of configuring a static random access memory (SRAM) bit cell for operation, an adaptive biasing device and semiconductor wafer testing system. In one embodiment, the method includes: (1) determining a performance characteristic of the SRAM bit cell on a wafer, (2) comparing the performance characteristic to a target and (3) configuring biasing circuitry associated with the SRAM bit cell based on the comparing.Type: ApplicationFiled: August 15, 2007Publication date: February 19, 2009Applicant: Texas Instruments IncorporatedInventors: Alice Wang, David Scott, Sumanth Gururajarao, Gordon Gammie, Sudha Thiruvengadam
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Patent number: 7474582Abstract: One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.Type: GrantFiled: December 12, 2006Date of Patent: January 6, 2009Assignee: Texas Instruments IncorporatedInventors: Hugh Thomas Mair, James Sangwon Song, Franck Benjamin Dahan, William Douglas Wilson, Norman LeRoy Culp, Sudha Thiruvengadam
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Publication number: 20080137444Abstract: One embodiment of the present invention includes a system for managing power of a memory array. The system comprises a comparator configured to compare a first voltage with a reference voltage. The first voltage can correspond to an operating voltage of at least one of a peripheral circuit associated with the memory array and a logic circuit configured to communicate with the peripheral circuit. The reference voltage can correspond to a minimum threshold voltage for read/write operations of the memory array. The system also comprises an output circuit configured to provide an output voltage to the memory array in response to an output of the comparator. The output voltage can be the greater of the operating voltage of the at least one of the peripheral circuit and the logic circuit and the minimum threshold voltage.Type: ApplicationFiled: December 12, 2006Publication date: June 12, 2008Inventors: Hugh Thomas Mair, James Sangwon Song, Franck Benjamin Dahan, William Douglas Wilson, Norman LeRoy Culp, Sudha Thiruvengadam
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Patent number: 7376038Abstract: A computer system including a control logic and a storage coupled to the control logic. The storage includes a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.Type: GrantFiled: March 21, 2006Date of Patent: May 20, 2008Assignee: Texas Instruments IncorporatedInventors: Sudha Thiruvengadam, Ramaprasath Vilangudipitchai, David B. Scott, Uming U. Ko, Alice Wang
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Publication number: 20070223294Abstract: A computer system comprising a control logic and a storage coupled to the control logic. The storage comprises a plurality of bitcells and bitlines used to transfer data between the control logic and the bitcells. The control logic provides an address of a target bitcell to the storage. Within a single clock cycle, the storage uses the address to activate the target bitcell, to precharge bitlines coupled to the target bitcell, and to access the target bitcell.Type: ApplicationFiled: March 21, 2006Publication date: September 27, 2007Applicant: Texas Instruments IncorporatedInventors: Sudha Thiruvengadam, Ramaprasath Vilangudipitchai, David Scott, Uming Ko, Alice Wang
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Patent number: 7236396Abstract: An SRAM array with a dummy cell row structure in which the SRAM array is divided into segments isolated by a row pattern of dummy cells. The dummy cell structure provides a continuous cell array at the lower cell patterning levels. The SRAM array includes a first and second array block each including an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.Type: GrantFiled: June 30, 2005Date of Patent: June 26, 2007Assignee: Texas Instruments IncorporatedInventors: Theodore W. Houston, David Barry Scott, Sudha Thiruvengadam
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Publication number: 20070002617Abstract: An SRAM array and a dummy cell row structure is discussed that permits an SRAM array to be divided into segments isolated by a row pattern of dummy cells. The dummy cell structure avoids the use of special OPC conditions at the power supply line and block boundaries by providing a continuous cell array at the lower cell patterning levels in an area efficient implementation. In one implementation, the SRAM array comprises a first and second array block each comprising an SRAM cell having a first layout configuration, one or more of the dummy cells having a second layout configuration arranged along the row pattern associated with a wordline of the SRAM array, a first power supply voltage line connected to the first array block, and a second different power supply voltage line connected to the second array block. The first and second power supply voltage lines of the array blocks are further connected to the one or more dummy cells.Type: ApplicationFiled: June 30, 2005Publication date: January 4, 2007Inventors: Theodore Houston, David Scott, Sudha Thiruvengadam
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Patent number: 5710780Abstract: Digital circuitry (11) in a data processing system (10) includes parallel signature analysis circuitry (49, 49A) having a sampling feature (51, 53, 89) which permits sampling any given signal on all clock phases of the digital circuitry.Type: GrantFiled: August 8, 1996Date of Patent: January 20, 1998Assignee: Texas Instruments IncorporatedInventor: Sudha Thiruvengadam
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Patent number: 5572536Abstract: Digital circuitry in a data processing system includes parallel signature analysis circuitry having a sampling feature which permits sampling any given signal on all clock phases of the digital circuitry. The parallel signature analysis circuitry provides for selective coupling of a target node to each of the respective inputs of a pair of serially-coupled latches.Type: GrantFiled: May 26, 1994Date of Patent: November 5, 1996Assignee: Texas Instruments IncorporatedInventor: Sudha Thiruvengadam