Patents by Inventor Sudhakar Bhat

Sudhakar Bhat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Systems and methods for testing processors
    Patent number: 6925584
    Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: August 2, 2005
    Assignee: Intel Corporation
    Inventors: Kiran A. Padwekar, Jesse Pan, Sudhakar Bhat
  • Systems and methods for testing processors
    Publication number: 20030196146
    Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.
    Type: Application
    Filed: April 30, 2003
    Publication date: October 16, 2003
    Applicant: Intel Corporation
    Inventors: Kiran A. Padwekar, Jesse Pan, Sudhakar Bhat
  • Systems and methods for testing processors
    Patent number: 6571359
    Abstract: Methods and systems of testing a processor are disclosed. A system includes a storage unit, a memory hierarchy, and a processor. The memory hierarchy is coupled to the storage element. The processor is coupled to the memory hierarchy. The processor reads instructions from the memory hierarchy. On a probe mode break, the processor initiates the transfer of original code of the memory hierarchy to the storage unit. Test code is loaded into the memory hierarchy. The test code is executed. The original code is loaded back into the memory hierarchy. Normal execution is resumed.
    Type: Grant
    Filed: December 13, 1999
    Date of Patent: May 27, 2003
    Assignee: Intel Corporation
    Inventors: Kiran A. Padwekar, Jesse Pan, Sudhakar Bhat