Abstract: An integrated, non-volatile memory protect register is provided for the memory array of a monolithic integrated circuit device. The memory array includes a plurality of programmable data storage registers, each having an associated address. The storage register addresses define the storage registers sequentially from an initial register in the array to a final register in the array. The memory protect register stores the address of a preselected storage register in the array. All registers in the array having addresses equal to or greater than the address of the preselected register are protected from any write operation. This address can be "locked" into the memory protect register to provide permanent data security to all protected registers.

Abstract: Circuitry for serial read memory access utilizing a random starting address is disclosed. Fast read access is provided without upsetting the original data pattern stored in the memory core if the sequential read is terminated in midstream. After the last memory address is reached, the access automatically rolls over to the first address. The circuit provides both random and sequential access functions and allows the memory to be used as a shift register of variable length.