Patents by Inventor Sudhakar Kale

Sudhakar Kale has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11947581
    Abstract: A plurality of personalized news feeds are generated from input feeds including digital content items based on a dynamic taxonomy data structure. Entities are extracted from the input feeds and relationship strengths are obtained for the extracted entities and the digital content items. The dynamic taxonomy data structure is updated with the extracted entities and entries for the digital content news items are included at the corresponding branches based on the relationship strengths. Attributes are obtained for the entities and those entities corresponding to the trending topics are identified. Personalized news feeds are generated including the digital content items listed under the entities. Digital content items are added or removed from the digital content feeds based on one or more entity attributes.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: April 2, 2024
    Assignee: ACCENTURE GLOBAL SOLUTIONS LIMITED
    Inventors: Srikanth G Rao, Tarun Singhal, Mathangi Sandilya, Issac Abraham Alummoottil, Raja Sekhar Velagapudi, Rahel James Kale, Ankur Garg, Jayaprakash Nooji Shekar, Omkar Sudhakar Deorukhkar, Veera Raghavan Valayaputhur
  • Patent number: 7337418
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design. Some embodiments of the structural regularity extraction component automatically generate a set of vectors for the logic design. A vector is a group of template instances that are identical in function and in structure. The vectors generated by the structural regularity extraction component are used by a floorplanning component. The floorplanning component provides a method of generating a circuit layout from the set of vectors. In some embodiments, each vectors corresponds to a row in the circuit layout.
    Type: Grant
    Filed: July 14, 2003
    Date of Patent: February 26, 2008
    Assignee: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Publication number: 20040010759
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.
    Type: Application
    Filed: July 14, 2003
    Publication date: January 15, 2004
    Applicant: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta
  • Patent number: 6594808
    Abstract: In some embodiments, a computer-aided design system comprises a functional regularity extraction component, a structural regularity extraction component and a floorplanning component. The functional regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the functional characteristics of a logic design. Some embodiments of the functional regularity extraction component automatically generate a set of templates to cover a circuit. A template is a representation of a subcircuit with at least two instances in the circuit. The templates generated by the functional regularity extraction component are used by a structural regularity extraction component. The structural regularity extraction component provides a method to extract regularity for circuits (and in particular datapath circuits) based on the structural characteristics of a logic design.
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: July 15, 2003
    Assignee: Intel Corporation
    Inventors: Sudhakar Kale, Amit Chowdhary, Phani Saripella, Naresh K. Sehgal, Rajesh Gupta