Patents by Inventor Sudhakar M. Reddy

Sudhakar M. Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for generating test pattern for semiconductor integrated circuit and method for testing semiconductor integrated circuit
    Patent number: 6799292
    Abstract: A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A test pattern is generated for the selected path so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a capture clock pulse is input to the circuit. Next, the test pattern generated is transformed into a normal scan pattern. Also, an expected output value, which should result from the test pattern input, is obtained. Then, the test pattern is input to the path under test and the resultant output value is compared to the expected value. In this manner, the path can be tested in such a manner as to see whether or not any hold error will occur.
    Type: Grant
    Filed: March 7, 2001
    Date of Patent: September 28, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Sudhakar M. Reddy, Seiji Kajihara
  • Method for generating test pattern for semiconductor integrated circuit and method for testing semiconductor integrated circuit
    Publication number: 20010029593
    Abstract: A path under test is selected from a semiconductor integrated circuit that has been designed by a scan method. A test pattern is generated for the selected path so that the path is sensitized and a signal, passing through the path, changes its level at a time before or after a capture clock pulse is input to the circuit. Next, the test pattern generated is transformed into a normal scan pattern. Also, an expected output value, which should result from the test pattern input, is obtained. Then, the test pattern is input to the path under test and the resultant output value is compared to the expected value. In this manner, the path can be tested in such a manner as to see whether or not any hold error will occur.
    Type: Application
    Filed: March 7, 2001
    Publication date: October 11, 2001
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Sadami Takeoka, Sudhakar M. Reddy, Seiji Kajihara