Patents by Inventor Sudhakar Mannapuram Reddy

Sudhakar Mannapuram Reddy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Scheduling the concurrent testing of multiple cores embedded in an integrated circuit
    Patent number: 6934897
    Abstract: Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.
    Type: Grant
    Filed: July 31, 2002
    Date of Patent: August 23, 2005
    Inventors: Nilanjan Mukherjee, Chien-Chung Tsai, Wu-Tung Cheng, Omer Ghazi Samman, Yahya M. Z. Mustafa, Paul J. Reuter, Yu Huang, Sudhakar Mannapuram Reddy
  • Scheduling the concurrent testing of multiple cores embedded in an integrated circuit
    Publication number: 20030191996
    Abstract: Methods are described for scheduling the concurrent testing of multiple cores embedded in an integrated circuit. Test scheduling is performed by formulating the problem as a bin-packing problem and using a modified two-dimensional or three-dimensional bin-packing heuristic. The tests of multiple cores are represented as functions of at least the integrated circuit pins used to test the core and the core test time. The representations may include a third dimension of peak power required to test the core. The test schedule is represented as a bin having dimensions of at least integrated circuit pins and integrated circuit test time. The bin may include a third dimension of peak power. The scheduling of the multiple cores is accomplished by fitting the multiple core test representations into the bin.
    Type: Application
    Filed: July 31, 2002
    Publication date: October 9, 2003
    Inventors: Nilanjan Mukherjee, Chien-Chung Tsai, Wu-Tung Cheng, Omer Ghazi Samman, Yahya M. Z. Mustafa, Paul J. Reuter, Yu Huang, Sudhakar Mannapuram Reddy