Patents by Inventor Sudhakar Otturu

Sudhakar Otturu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10552613
    Abstract: A computing device that implements a secure and transparent firmware update process is provided. The computing device includes a secure memory area and a secure device that separately executes firmware updates in parallel with other processes executed by a CPU. The secure memory area may be allocated by the CPU and/or a memory controller using any of a variety of memory protection techniques. System software executed by the CPU receives update firmware requests from a trusted source, stores a firmware payload included in these requests in the secure memory area, and executes the next scheduled process. Firmware executed by the secure device retrieves the firmware payload from the secure memory area, authenticates the firmware payload, and applies the firmware payload to a firmware storage device. The secure device performs these acts transparently from the point of view of the CPU, these avoiding consumption of resources of the CPU.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: February 4, 2020
    Assignee: INTEL CORPORATION
    Inventors: Krishnakumar Narasimhan, Sudhakar Otturu, Karunakara Kotary, Vincent J. Zimmer
  • Patent number: 10389851
    Abstract: In one embodiment, a system includes a display, a non-volatile memory to store one or more system software images, a processor to execute at least one of the one or more system software images, and a security engine to perform security applications. The security engine may include a first logic to receive a download package from a host computing system and store the download package in a first memory, authenticate the download package, and execute the download package to download and store a first system software image into the non-volatile memory. In addition, a second logic of the system may be configured to disable at least the display during the first system software image download and store. Other embodiments are described and claimed.
    Type: Grant
    Filed: September 17, 2015
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Krishna Kumar Ganesan, Sudhakar Otturu, Nicholas J. Adams
  • Patent number: 10282538
    Abstract: Technologies to enable, disable and control hardware subscription features. Computing devices communicate over a network to a subscription server to provide hardware platform information for each of the computing devices. As the subscription server receives hardware platform information, the subscription server determines the hardware features that are enabled, and further determines what hardware subscription options are available for each of the computing devices. When a hardware subscription option is selected/purchased by a computing device, subscription server provides a pre-boot update mechanism, such as a Unified Extensible Firmware Interface (UEFI) capsule, to act as a boot level program that enables hardware features on the computing device. Hardware subscription features are also securely protected using cryptographic engine modules.
    Type: Grant
    Filed: December 27, 2014
    Date of Patent: May 7, 2019
    Assignee: Intel Corporation
    Inventors: Sudhakar Otturu, Krishna Kumar Ganesan, Erik Holt
  • Publication number: 20190095623
    Abstract: A computing device that implements a secure and transparent firmware update process is provided. The computing device includes a secure memory area and a secure device that separately executes firmware updates in parallel with other processes executed by a CPU. The secure memory area may be allocated by the CPU and/or a memory controller using any of a variety of memory protection techniques. System software executed by the CPU receives update firmware requests from a trusted source, stores a firmware payload included in these requests in the secure memory area, and executes the next scheduled process. Firmware executed by the secure device retrieves the firmware payload from the secure memory area, authenticates the firmware payload, and applies the firmware payload to a firmware storage device. The secure device performs these acts transparently from the point of view of the CPU, these avoiding consumption of resources of the CPU.
    Type: Application
    Filed: September 26, 2017
    Publication date: March 28, 2019
    Applicant: INTEL CORPORATION
    Inventors: Krishnakumar Narasimhan, Sudhakar Otturu, Karunakara Kotary, Vincent J. Zimmer
  • Patent number: 9606853
    Abstract: In an embodiment, a computing device may include a memory device that may be rendered unusable after a certain number of operations are performed on the memory device. The computing device may incorporate one or more techniques for protecting the memory device. Processing logic contained in the computing device may be configured to implement the techniques. The techniques may include, for example, acquiring a request to write or erase information stored in a memory device contained in a first computing device, saving the request for execution after a user visible event has been generated on the first computing device, generating the user visible event on the first computing device, and executing the saved request after the user visible event has been generated. In addition, the techniques may include reporting the request. The request may be reported to, for example, an anti-malware agent.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: March 28, 2017
    Assignee: Intel Corporation
    Inventors: Nitin V. Sarangdhar, Sudhakar Otturu
  • Publication number: 20170083305
    Abstract: In one embodiment, a system includes a display, a non-volatile memory to store one or more system software images, a processor to execute at least one of the one or more system software images, and a security engine to perform security applications. The security engine may include a first logic to receive a download package from a host computing system and store the download package in a first memory, authenticate the download package, and execute the download package to download and store a first system software image into the non-volatile memory. In addition, a second logic of the system may be configured to disable at least the display during the first system software image download and store. Other embodiments are described and claimed.
    Type: Application
    Filed: September 17, 2015
    Publication date: March 23, 2017
    Inventors: Krishna Kumar Ganesan, Sudhakar Otturu, Nicholas J. Adams
  • Publication number: 20160188868
    Abstract: Technologies to enable, disable and control hardware subscription features. Computing devices communicate over a network to a subscription server to provide hardware platform information for each of the computing devices. As the subscription server receives hardware platform information, the subscription server determines the hardware features that are enabled, and further determines what hardware subscription options are available for each of the computing devices. When a hardware subscription option is selected/purchased by a computing device, subscription server provides a pre-boot update mechanism, such as a Unified Extensible Firmware Interface (UEFI) capsule, to act as a boot level program that enables hardware features on the computing device. Hardware subscription features are also securely protected using cryptographic engine modules.
    Type: Application
    Filed: December 27, 2014
    Publication date: June 30, 2016
    Inventors: Sudhakar Otturu, Krishna Kumar Ganesan, Erik Holt
  • Publication number: 20150278003
    Abstract: In an embodiment, a computing device may include a memory device that may be rendered unusable after a certain number of operations are performed on the memory device. The computing device may incorporate one or more techniques for protecting the memory device. Processing logic contained in the computing device may be configured to implement the techniques. The techniques may include, for example, acquiring a request to write or erase information stored in a memory device contained in a first computing device, saving the request for execution after a user visible event has been generated on the first computing device, generating the user visible event on the first computing device, and executing the saved request after the user visible event has been generated. In addition, the techniques may include reporting the request. The request may be reported to, for example, an anti-malware agent.
    Type: Application
    Filed: March 28, 2014
    Publication date: October 1, 2015
    Inventors: Nitin V. Sarangdhar, Sudhakar Otturu
  • Patent number: 6976188
    Abstract: The present invention provides systems and methods for creating a customized POST program for use in a computing system. Specifically, the system of the present invention includes each of the routines for POST stored in different locations with associated calls for locating and running the routines. Each routine includes an instruction section containing editable data that indicates the sequence that the routine should be run in POST in relation to the other routines. The system further includes a POST program builder that builds a POST program that includes calls to each routine. The calls for each routine are stored in sequence in the POST program based on the information from the instruction segment associated with each routine.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: December 13, 2005
    Assignee: American Megatrends, Inc.
    Inventors: Oleksandr Podgorsky, Sudhakar Otturu
  • Publication number: 20030110415
    Abstract: The present invention provides systems and methods for creating a customized POST program for use in a computing system. Specifically, the system of the present invention includes each of the routines for POST stored in different locations with associated calls for locating and running the routines. Each routine includes an instruction section containing editable data that indicates the sequence that the routine should be run in POST in relation to the other routines. The system further includes a POST program builder that builds a POST program that includes calls to each routine. The calls for each routine are stored in sequence in the POST program based on the information from the instruction segment associated with each routine.
    Type: Application
    Filed: November 4, 2002
    Publication date: June 12, 2003
    Inventors: Oleksandr Podgorsky, Sudhakar Otturu