Abstract: A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry in the fetch ahead branch target buffer corresponds to one branch instruction and comprises a data portion identifying the target address of that branch instruction. In various examples, an entry also comprises a tag portion which stores data identifying the fetch pointer by which the entry is indexed. Branch prediction is performed by matching an index generated using a received fetch pointer to the tag portions to identify a matching entry and then determining the target address for the branch instruction from the data portion of the matching entry.

Abstract: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

Abstract: A system and method process atomic instructions. A processor system includes a load store unit (LSU), first and second registers, a memory interface, and a main memory. In response to a load link (LL) instruction, the LSU loads first data from memory into the first register and sets an LL bit (LLBIT) to indicate a sequence of atomic instructions is being executed. The LSU further loads second data from memory into the second register in response to a load (LD) instruction. The LSU places a value of the second register into the memory interface in response to a store conditional coupled (SCX) instruction. When the LLBIT is set and in response to a store (SC) instruction, the LSU places a value of the second register into the memory interface and commits the first and second register values in the memory interface into the main memory when the LLBIT is set.

Abstract: An apparatus, system, and method provide a way for tracking the age of items stored within a queue. An apparatus includes an item storage array and an array of age-tracking bits. The item storage array stores data of valid items stored in the queue. The array of age-tracking bits is associated with valid items stored in the queue. Age-tracking bits associated with a subset of items in the queue are set to a first value when the subset of items is older than other items in the queue. The younger items in the queue correspond to the age-tracking bits set to the first value. Other age-tracking bits associated with the subset of items in the queue are set to a second value when the subset of items is younger than other items in the queue. The older queue items correspond to the age-tracking bits set to the second value.

Abstract: A fetch ahead branch target buffer is used by a branch predictor to determine a target address for a branch instruction based on a fetch pointer for a previous fetch bundle, i.e. a fetch bundle which is fetched prior to a fetch bundle which includes the branch instruction. An entry in the fetch ahead branch target buffer corresponds to one branch instruction and comprises a data portion identifying the target address of that branch instruction. In various examples, an entry also comprises a tag portion which stores data identifying the fetch pointer by which the entry is indexed. Branch prediction is performed by matching an index generated using a received fetch pointer to the tag portions to identify a matching entry and then determining the target address for the branch instruction from the data portion of the matching entry.

Abstract: A processor includes a register and a load store unit (LSU). The LSU loads data into the register from a memory. When in little endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing byte memory addresses from a first end (right end) of the register to a second end (left end) of the register. When in big endian mode, bytes from sequentially increasing memory addresses are loaded in order of corresponding sequentially increasing memory addresses from the second end (left end) of the register to the first end (right) of the register. Therefore, regardless of operating in little or big endian mode, the data in the register has its most significant byte on its left side and its least significant byte on its right side which simplifies the execution of SIMD instructions because the data is aligned the same for both endian modes.