Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to pause memory sub-system operations in response to a critical event. The memory sub-system controller can include a front-end (FE) device that stores critical event trigger data in trigger event logic registers. Upon detecting that operations of the memory sub-system, such as command latencies, correspond to the critical event trigger data, the FE device performs pause operations, including storing a state of the memory sub-system and transmitting an interrupt signal to the memory sub-system controller, such as a CPU, to initiate debugging operations.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to pause memory sub-system operations in response to a critical event. The memory sub-system controller can include a front-end (FE) device that stores critical event trigger data in trigger event logic registers. Upon detecting that operations of the memory sub-system, such as command latencies, correspond to the critical event trigger data, the FE device performs pause operations, including storing a state of the memory sub-system and transmitting an interrupt signal to the memory sub-system controller, such as a CPU, to initiate debugging operations.

Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to pause memory sub-system operations in response to a critical event. The memory sub-system controller can include a front-end (FE) device that stores critical event trigger data in trigger event logic registers. Upon detecting that operations of the memory sub-system, such as command latencies, correspond to the critical event trigger data, the FE device performs pause operations, including storing a state of the memory sub-system and transmitting an interrupt signal to the memory sub-system controller, such as a CPU, to initiate debugging operations.