Abstract: An improved metal stack strategy is disclosed. A first aspect of the present invention provides a method for defining an optimized metal stack option based on critical path information. The method and system use interconnect data from timing critical paths from at least one previous design to generate interconnect statistical data. The interconnect statistical data is then used to vary physical properties of interconnects in a current design during simulation until optimum performance is achieved. A second aspect of the present invention provides a method for reusing an ASIC core design with different metal stack options. This method defines x common metal layers across at least two metal stack options, where interconnects on each of the metal layers have common physical and electrical characteristics. An ASIC core design based on the x common metal layers is also defined, thereby making the ASIC core compatible with the different metal stack options.

Abstract: A power distribution system for distributing external power across a die is disclosed, wherein the die has multiple sides, and a plurality of power bond pads located along each of the sides for receiving an external power signal. The system and method include patterning a plurality of straight power lines that form a single-layer power mesh diagonally across the die to connect the power bond pads that are located on two different sides of the die. As an alternative to the first embodiment, the diagonal power lines are patterned in a stair-step configuration for ease of manufacturing.

Abstract: A semiconductor memory layout definition for connection to a power supply bus in an integrated circuit layout pattern. The layout definition includes an outline and a plurality of power supply conductor segments within the outline. At least one of the power supply conductor segments has a direct strap identifier which indicates a desired attachment to the power supply bus. The direct strap identifier is passed to a routing design tool which routes a direct strap conductor from the power supply bus to the power supply conductor segments having the direct strap identifier.