Abstract: An optical device for characterizing flicker from an ambient light source is disclosed. The device comprises a radiation-sensitive device configured to vary a current in response to incident radiation, a second or higher-order modulator configured to output data corresponding to the current, and processing circuitry configured to provide a real-time characterization of flicker in the incident radiation based upon an analysis of changes in the data. Also disclosed is an associated method of characterizing flicker from an ambient light source.

Abstract: An ambient light sensor is provided that includes a sensor input having a delta-sigma analogue to digital converter. The delta-sigma analogue to digital converter includes a switched capacitor, a common mode voltage source, a reference voltage source, and a switch network. In a first clock phase, the switch network connects the switched capacitor to charge it to either a sum or difference voltage. In a second clock phase, the switch network connects the switched capacitor to transfer charge into a summing junction. A controller controls the switch network in response to a comparator output to connect the switched capacitor to either the common mode voltage or the reference voltage while in the first clock phase.

Abstract: A sensor circuit comprising a sensor input includes a delta-sigma analogue to digital converter. The delta-sigma analogue to digital converter includes a switched capacitor, a common mode voltage source, a reference voltage source, and a switch network. The switch network, in a first clock phase, connects the switched capacitor to charge it to either a sum or difference voltage, and in a second clock phase connects the switched capacitor to transfer charge into a summing junction. A controller controls the switch network responsive to a comparator output to selectively connect the switched capacitor to one of the common mode voltage and the reference voltage in the first clock phase. Implementations of the sensor circuit transfer charge every clock cycle and have low noise and high sensitivity.

Abstract: A sensor arrangement for light sensing for light-to-frequency conversion. The sensor arrangement includes a photodiode, an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK1), and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing the digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of chopping switches coupled to a first amplifier, a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

Abstract: A sensor arrangement for light sensing for light-to-frequency conversion. The sensor arrangement includes a photodiode, an analog-to-digital converter (ADC) operable to perform a chopping technique in response to a first clock signal (CLK1), and convert a photocurrent (IPD) into a digital comparator output signal (LOUT). The ADC includes a sensor input coupled to the photodiode, an output for providing the digital comparator output signal (LOUT), an integrator including an integrator input coupled to the sensor input and operable to receive an integrator input signal, a first set of chopping switches coupled to a first amplifier, a second set of chopping switches electrically coupled to an output of the first amplifier and electrically coupled to input terminals of a second amplifier, and an integrator output providing an integrator output signal (OPOUT).

Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

Abstract: An analog-to-digital converter (10) comprises a first and a second sampling capacitor (24, 25), a first integrator (26), a first and a second input switch (31, 32) coupling a first input terminal (11) and a common mode terminal (39) to a first electrode of the first sampling capacitor (24), a third and a fourth input switch (33, 34) coupling a second input terminal (12) and the common mode terminal (39) to a first electrode of the second sampling capacitor (25), a fifth and a sixth input switch (35, 36) coupling a second electrode of the first sampling capacitor (24) to an amplifier common mode terminal (40) and the first integrator input (27), and a seventh and an eighth input switch (37, 38) coupling a second electrode of the second sampling capacitor (25) to the amplifier common mode terminal (40) and the second integrator input (28).

Abstract: The invention relates to a cell balancing module, particularly for voltage balancing of a stack of batteries. The cell balancing module comprises an interface (SPI, VrefH, VrefL) to input a coded reference voltage (Vref) and input nodes (In1, . . . , InN) for connecting a stack of energy storage cells (BAT1, . . . , BATn). A switching unit (SW) is connected to each of the input nodes (In1, . . . , InN) and a local balancing unit (loc) coupled to the switching unit (SW) and the interface (SPI, VrefH, VrefL). The local balancing unit (loc) is designed to compare the coded reference voltage (Vref) with cell voltages (VBAT1, . . . , VBATn) of the stack of energy storage cells (BAT1, . . . , BATn) to be connected and to charge balance the stack of energy storage cells (BAT1, . . . , BATn) to be connected depending on the comparison of coded reference voltage (Vref) and cell voltages (VBAT1, . . . , VBATn).

Abstract: The invention relates to a cell balancing module, particularly for voltage balancing of a stack of batteries. The cell balancing module comprises an interface (SPI, VrefH, VrefL) to input a coded reference voltage (Vref) and input nodes (In1, . . . , InN) for connecting a stack of energy storage cells (BAT1, . . . , BATn). A switching unit (SW) is connected to each of the input nodes (In1, . . . , InN) and a local balancing unit (loc) coupled to the switching unit (SW) and the interface (SPI, VrefH, VrefL). The local balancing unit (loc) is designed to compare the coded reference voltage (Vref) with cell voltages (VBAT1, . . . , VBATn) of the stack of energy storage cells (BAT1, . . . , BATn) to be connected and to charge balance the stack of energy storage cells (BAT1, . . . , BATn) to be connected depending on the comparison of coded reference voltage (Vref) and cell voltages (VBAT1, . . . , VBATn).