Patents by Inventor Sudhanshu Khanna
Sudhanshu Khanna has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11953969Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: GrantFiled: August 17, 2021Date of Patent: April 9, 2024Assignee: Texas Instruments IncorporatedInventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 11914545Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.Type: GrantFiled: December 29, 2021Date of Patent: February 27, 2024Assignee: Texas Instruments IncorporatedInventors: Andreas Waechter, Mark Jung, Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 11860686Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.Type: GrantFiled: October 5, 2022Date of Patent: January 2, 2024Assignee: Texas Instruments IncorporatedInventors: Atul Ramakant Lele, Dirk Preikszat, Sudhanshu Khanna, John Joseph Seibold
-
Patent number: 11847430Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: GrantFiled: November 8, 2021Date of Patent: December 19, 2023Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
-
Publication number: 20230025885Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output an altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.Type: ApplicationFiled: October 5, 2022Publication date: January 26, 2023Inventors: Atul Ramakant Lele, Dirk Preikszat, Sudhanshu Khanna, John Joseph Seibold
-
Patent number: 11467622Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.Type: GrantFiled: February 23, 2021Date of Patent: October 11, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Atul Ramakant Lele, Dirk Preikszat, Sudhanshu Khanna, John Joseph Seibold
-
Publication number: 20220269304Abstract: A clock oscillator control circuit is provided. The clock oscillator control circuit includes a signal processor configured to receive a composite clock request signal and output a altered composite clock request signal. The clock oscillator control circuit also includes logic circuitry configured to receive the altered composite clock request signal from the signal processor and a clock oscillator valid signal from a clock oscillator, and to output set and reset signals based on the altered composite clock request signal and the clock oscillator valid signal. The clock oscillator control circuit further includes a set-reset latch configured to receive the set and reset signals from the logic circuitry and to output an enable signal to the clock oscillator.Type: ApplicationFiled: February 23, 2021Publication date: August 25, 2022Inventors: Atul Ramakant Lele, Dirk Preikszat, Sudhanshu Khanna, John Joseph Seibold
-
Patent number: 11393971Abstract: An improved differential sensor and corresponding apparatus implementing same. The differential sensor includes a substrate, an amplifier coupled to the substrate, and a plurality of highly-matched piezoelectric capacitors formed onto the substrate. A first set of the highly-matched piezoelectric capacitors are electrically coupled to a non-inverting input of the amplifier, and a second set of the highly-matched piezoelectric capacitors are electrically coupled to an inverting input of the amplifier to form an open loop differential amplifier.Type: GrantFiled: November 27, 2018Date of Patent: July 19, 2022Assignee: Texas Instruments IncorporatedInventors: Sudhanshu Khanna, Michael Zwerg, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Publication number: 20220121608Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.Type: ApplicationFiled: December 29, 2021Publication date: April 21, 2022Inventors: Andreas WAECHTER, Mark JUNG, Steven Craig BARTLING, Sudhanshu KHANNA
-
Publication number: 20220115048Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.Type: ApplicationFiled: December 22, 2021Publication date: April 14, 2022Inventors: Steven Craig Bartling, Sudhanshu Khanna
-
Publication number: 20220057996Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: ApplicationFiled: November 8, 2021Publication date: February 24, 2022Inventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
-
Patent number: 11243903Abstract: Configuration states for a computing device and/or associated peripherals (“profiles”) are stored in one or more non-volatile logic (“NVL”) arrays. Using the non-volatile sub-system for the computing device, triggers for reconfiguration of the respective device or peripherals are provided to an NVL array controller, which controls provision of the new profile(s) for the respective device or peripherals over a dedicated bus to a configuration register that stores the active profiles for the device and associated peripherals.Type: GrantFiled: October 21, 2019Date of Patent: February 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Andreas Waechter, Mark Jung, Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 11244710Abstract: Design and operation of a processing device is configurable to optimize wake-up time and peak power cost during restoration of a machine state from non-volatile storage. The processing device includes a plurality of non-volatile logic element arrays configured to store a machine state represented by a plurality of volatile storage elements of the processing device. A stored machine state is read out from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements. During manufacturing, a number of rows and a number of bits per row in non-volatile logic element arrays are based on a target wake up time and a peak power cost. In another approach, writing data to or reading data of the plurality of non-volatile arrays can be done in parallel, sequentially, or in any combination to optimize operation characteristics.Type: GrantFiled: April 4, 2016Date of Patent: February 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Craig Bartling, Sudhanshu Khanna
-
Publication number: 20210389174Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: ApplicationFiled: August 31, 2021Publication date: December 16, 2021Inventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Patent number: 11200030Abstract: Disclosed examples include non-volatile counter systems to generate and store a counter value according to a sensor pulse signal, and power circuits to generate first and second supply voltage signals to power first and second power domain circuits using power from the sensor pulse signal, including a switch connected between first and second power domain supply nodes, a boost circuit, and a control circuit to selectively cause the switch to disconnect the first and second power domain circuits from one another after the first supply voltage signal rises above a threshold voltage in a given pulse of the sensor pulse signal, and to cause the boost circuit to boost the second supply voltage signal after the regulator output is disconnected from the second power domain supply node in the given pulse.Type: GrantFiled: December 11, 2019Date of Patent: December 14, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Sudhanshu Khanna, Hao Meng, Michael Zwerg, Christy Leigh She, Steven Craig Bartling
-
Publication number: 20210373647Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: ApplicationFiled: August 17, 2021Publication date: December 2, 2021Inventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 11132050Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.Type: GrantFiled: June 25, 2019Date of Patent: September 28, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Michael Zwerg, Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 11105676Abstract: In described examples, each node between adjacent capacitive elements of a stack of series-coupled capacitive elements is biased during a reset mode, where each of the capacitive elements includes piezoelectric material. A strain-induced voltage is generated across each of the capacitive elements. Each of the strain-induced voltages is combined to generate a piezoelectric-responsive output signal during a sensing mode at a time different from the time of the reset mode.Type: GrantFiled: November 14, 2018Date of Patent: August 31, 2021Assignee: Texas Instruments IncorporatedInventors: Michael Zwerg, Sudhanshu Khanna, Steven C. Bartling, Brian Elies, Krishnasawamy Nagaraj, Wei-Yan Shih
-
Patent number: 10930328Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.Type: GrantFiled: November 5, 2019Date of Patent: February 23, 2021Assignee: Texas Instruments IncorporatedInventors: Steven Craig Bartling, Sudhanshu Khanna
-
Patent number: 10902895Abstract: A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.Type: GrantFiled: June 15, 2017Date of Patent: January 26, 2021Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Steven Craig Bartling, Sudhanshu Khanna