Abstract: The present disclosure describes a system with an antenna, a signal generator, data converters, and an aggregator circuit. The antenna is configured to provide an input signal to the data converters. The signal generator is configured to generate a random binary sequence received by the data converters. The data converters include an analog circuit and a digital circuit configured to sample positive and negative polarities of the input signal based on the random binary sequence, reducing an offset tone in an output spectrum produced by the aggregator circuit.

Abstract: A high input impedance switched capacitor amplifier is disclosed. The switched capacitor amplifier includes at least a first buffer circuit configured to charge a first plurality of capacitors during a first time period. A switch circuit is configured to, during a second time period, cause a modification of an amount of charge stored on one of the first plurality of capacitors by coupling an input signal directly to the one of first plurality of capacitors. An amplifier circuit is configured to, based on a sampling voltage present on one of the first plurality of capacitors, generate an output signal.

Abstract: The present disclosure describes a system with an antenna, a signal generator, data converters, and an aggregator circuit. The antenna is configured to provide an input signal to the data converters. The signal generator is configured to generate a random binary sequence received by the data converters. The data converters include an analog circuit and a digital circuit configured to sample positive and negative polarities of the input signal based on the random binary sequence, reducing an offset tone in an output spectrum produced by the aggregator circuit.

Abstract: An interleaved digital-to-analog converter (DAC) system may include a first sub-DAC and a second sub-DAC and may be configured to provide both a converter output signal and a calibration output signal. The converter output signal may be provided by adding the first sub-DAC output signal and the second sub-DAC output signal. The calibration output signal may be provided by subtracting one of the first and second sub-DAC output signals from the other. The calibration output signal may be used as feedback to adjust the phase of one of the sub-DACs relative to the other, to promote phase matching their output signals.

Abstract: An integrated circuit is disclosed to bypass transients between first and second nodes. The circuit includes a first bypass capacitor implemented as a metal oxide semiconductor (MOS) transistor and coupled to a first node; and a switch coupled to the first bypass capacitor and the second node, the switch preventing leakage current from passing through the first bypass capacitor during power down.