Patents by Inventor Sudharshanan Raghunathan
Sudharshanan Raghunathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230076218Abstract: Methods related to improving a simulation processes and solutions (e.g., retargeted patterns) associated with manufacturing of a chip. A method includes obtaining a plurality of dose-focus settings, and a reference distribution based on measured values of a characteristic of a printed pattern associated with each setting of the plurality of dose-focus settings. The method further includes, based on an adjustment model and the plurality of dose-focus settings, determining a probability density function (PDF) of the characteristic such that an error between the PDF and the reference distribution is reduced. The PDF can be a function of the adjustment model and variance associated with dose, the adjustment model being configured to change a proportion of non-linear dose sensitivity contribution to the PDF. A process window can be adjusted based on the determined PDF of the characteristic.Type: ApplicationFiled: February 18, 2021Publication date: March 9, 2023Applicant: ASML NETHERLANDS B.V.Inventors: Koenraad VAN INGEN SCHENAU, Abraham SLACHTER, Vadim Yourievich TIMOSHKOV, Marleen KOOIMAN, Marie-Claire VAN LARE, Hermanus Adrianus DILLEN, Stefan HUNSCHE, Luis Alberto Colina Sant COLINA, Aiqin JIANG, Fuming WANG, Sudharshanan RAGHUNATHAN
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Patent number: 10962887Abstract: A method for determining one or more optimized values of an operational parameter of a sensor system configured for measuring a property of a substrate is disclosed the method including: determining a quality parameter for a plurality of substrates; determining measurement parameters for the plurality of substrates obtained using the sensor system for a plurality of values of the operational parameter; comparing a substrate to substrate variation of the quality parameter and a substrate to substrate variation of a mapping of the measurement parameters; and determining the one or more optimized values of the operational parameter based on the comparing.Type: GrantFiled: November 18, 2019Date of Patent: March 30, 2021Assignee: ASML Netherlands B.V.Inventors: Patricius Aloysius Jacobus Tinnemans, Edo Maria Hulsebos, Henricus Johannes Lambertus Megens, Sudharshanan Raghunathan, Boris Menchtchikov, Ahmet Koray Erdamar, Loek Johannes Petrus Verhees, Willem Seine Christian Roelofs, Wendy Johanna Martina Van De Ven, Hadi Yagubizade, Hakki Ergün Cekli, Ralph Brinkhof, Tran Thanh Thuy Vu, Maikel Robert Goosen, Maaike Van't Westeinde, Weitian Kou, Manouk Rijpstra, Matthijs Cox, Franciscus Godefridus Casper Bijnen
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Publication number: 20200081356Abstract: A method for determining one or more optimized values of an operational parameter of a sensor system configured for measuring a property of a substrate is disclosed the method comprising: determining a quality parameter for a plurality of substrates; determining measurement parameters for the plurality of substrates obtained using the sensor system for a plurality of values of the operational parameter; comparing a substrate to substrate variation of the quality parameter and a substrate to substrate variation of a mapping of the measurement parameters; and determining the one or more optimized values of the operational parameter based on the comparing.Type: ApplicationFiled: November 18, 2019Publication date: March 12, 2020Applicant: ASML NETHERLANDS B.V.Inventors: Patricius Aloysius Jacobus TINNEMANS, Edo Maria HULSEBOS, Henricus Johannes Lambertus MEGENS, Sudharshanan RAGHUNATHAN, Boris MENCHTCHIKOV, Ahmet Koray ERDAMAR, Loek Johannes Petrus VERHEES, Willem Seine Christian ROELOFS, Wendy Johanna Martina VAN DE VEN, Hadi YAGUBIZADE, Hakki Ergün CEKLI, Ralph BRINKHOF, Tran Thanh Thuy VU, Maikel Robert GOOSEN, Maaike VAN'T WESTEINDE, Weitian KOU, Manouk RIJPSTRA, Matthijs COX, Franciscus Godefridus Casper BIJNEN
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Patent number: 10559503Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.Type: GrantFiled: October 9, 2017Date of Patent: February 11, 2020Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
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Patent number: 10527958Abstract: A method for determining one or more optimized values of an operational parameter of a sensor system configured to measure a property of a substrate is disclosed. The method includes: determining a quality parameter for a plurality of substrates; determining measurement parameter values for the plurality of substrates using the sensor system for a plurality of values of the operational parameter; comparing a substrate to substrate variation of the quality parameter and a substrate to substrate variation of a mapping of the measurement parameter values; and determining the one or more optimized values of the operational parameter based on the comparing.Type: GrantFiled: September 17, 2018Date of Patent: January 7, 2020Assignee: ASML Netherlands B.V.Inventors: Patricius Aloysius Jacobus Tinnemans, Edo Maria Hulsebos, Henricus Johannes Lambertus Megens, Sudharshanan Raghunathan, Boris Menchtchikov, Ahmet Koray Erdamar, Loek Johannes Petrus Verhees, Willem Seine Christian Roelofs, Wendy Johanna Martina Van De Ven, Hadi Yagubizade, Hakki Ergün Cekli, Ralph Brinkhof, Tran Thanh Thuy Vu, Maikel Robert Goosen, Maaike Van't Westeinde, Weitian Kou, Manouk Rijpstra, Matthijs Cox, Franciscus Godefridus Casper Bijnen
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Publication number: 20190094721Abstract: A method for determining one or more optimized values of an operational parameter of a sensor system configured to measure a property of a substrate is disclosed. The method includes: determining a quality parameter for a plurality of substrates; determining measurement parameter values for the plurality of substrates using the sensor system for a plurality of values of the operational parameter; comparing a substrate to substrate variation of the quality parameter and a substrate to substrate variation of a mapping of the measurement parameter values; and determining the one or more optimized values of the operational parameter based on the comparing.Type: ApplicationFiled: September 17, 2018Publication date: March 28, 2019Applicant: ASML NETHERLANDS B.V.Inventors: Patricius Aloysius Jacobus TINNEMANS, Edo Maria HULSEBOS, Henricus Johannes Lambertus MEGENS, Sudharshanan RAGHUNATHAN, Boris MENCHTCHIKOV, Ahmet Koray ERDAMAR, Loek Johannes Petrus VERHEES, Willem Seine Christian ROELOFS, Wendy Johanna Martina VAN DE VEN, Hadi YAGUBIZADE, Hakki Ergün CEKLI, Ralph BRINKHOF, Tran Thanh Thuy VU, Maikel Robert GOOSEN, Maaike VAN'T WESTEINDE, Weitian KOU, Manouk RIJPSTRA, Matthijs COX, Franciscus Godefridus Casper BIJNEN
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Patent number: 10236350Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.Type: GrantFiled: March 11, 2016Date of Patent: March 19, 2019Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
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Publication number: 20180033701Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.Type: ApplicationFiled: October 9, 2017Publication date: February 1, 2018Applicant: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
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Patent number: 9852984Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.Type: GrantFiled: July 12, 2016Date of Patent: December 26, 2017Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
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Patent number: 9818651Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.Type: GrantFiled: March 11, 2016Date of Patent: November 14, 2017Assignee: GlobalFoundries Inc.Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
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Publication number: 20170263715Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device. A gate structure comprising a gate spacer on a semiconductor wafer is formed. A self-aligned contact (SAC) cap is formed over the gate structure. A TS structure is formed. At least one M0 metal structure void is formed. At least one CB structure void adjacent the M0 metal structure void is formed. An etch process is performed the M0 and CB structures voids to the gate structure. At least one CA structure void adjacent the CB structure void is formed. The M0, CB, and CA structure voids are metallized.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Inventors: Guillaume Bouche, Tuhin Guha Neogi, Sudharshanan Raghunathan, Andy Chi-Hung Wei, Jason Eugene Stephens, Vikrant Kumar Chauhan, David Michael Permana
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Publication number: 20170263506Abstract: At least one method, apparatus and system disclosed herein for forming a finFET device having a pass-through structure. A first gate structure and a second gate structure are formed on a semiconductor wafer. A first active area is formed on one end of the first and second gate structures. A second active area is formed on the other end of the first and second gate structures. A trench silicide (TS) structure self-aligned to the first and second gate structures is formed. The TS structure is configured to operatively couple the first active area to the second active area.Type: ApplicationFiled: March 11, 2016Publication date: September 14, 2017Applicant: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Tuhin Guha Neogi, Andy Chi-Hung Wei, Jia Zeng, Jongwook Kye, Jason Eugene Stephens, Irene Yuh-Ling Lin, Sudharshanan Raghunathan, Lei Yuan
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Publication number: 20160329278Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.Type: ApplicationFiled: April 21, 2016Publication date: November 10, 2016Inventors: Guillaume BOUCHE, Andy WEI, Sudharshanan RAGHUNATHAN
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Publication number: 20160322298Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.Type: ApplicationFiled: July 12, 2016Publication date: November 3, 2016Inventors: Guillaume BOUCHE, Andy WEI, Sudharshanan RAGHUNATHAN
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Patent number: 9478506Abstract: Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.Type: GrantFiled: March 6, 2013Date of Patent: October 25, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Richard A. Farrell, Gerard M. Schmid, Sudharshanan Raghunathan
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Patent number: 9425097Abstract: A method of lithographically cutting a Mx line before the Mx line is lithographically defined by patterning and the resulting 2DSAV device are provided. Embodiments include forming an a-Si dummy metal layer over a SiO2 layer; forming a first softmask stack over the a-Si dummy metal layer; patterning a plurality of vias through the first softmask stack down to the SiO2 layer; removing the first soft mask stack; forming first and second etch stop layers over the a-Si dummy metal layer, the first etch stop layer formed in the plurality of vias; forming a-Si mandrels on the second etch stop layer; forming oxide spacers on opposite sides of each a-Si mandrel; removing the a-Si mandrels; forming a-Si dummy metal lines in the a-Si dummy metal layer below the oxide spacers; and forming a SiOC layer between the a-Si dummy metal lines.Type: GrantFiled: April 29, 2015Date of Patent: August 23, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
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Patent number: 9362165Abstract: A method of forming 2D self-aligned vias before forming a subsequent metal layer and reducing capacitance of the resulting device and the resulting device are provided. Embodiments include forming dummy metal lines in a SiOC layer and extending in a first direction; replacing the dummy metal lines with metal lines, each metal line having a nitride cap; forming a softmask stack over the nitride cap and the SiOC layer; patterning a plurality of vias through the softmask stack down to the metal lines, the plurality of vias self-aligned along a second direction; removing the softmask stack; forming second dummy metal lines over the metal lines and extending in the second direction; forming a second SiOC layer between the dummy second metal lines on the SiOC layer; and replacing the dummy second metal lines with second metal lines, the second metal lines electrically connected to the metal lines through a via.Type: GrantFiled: May 8, 2015Date of Patent: June 7, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Guillaume Bouche, Andy Wei, Sudharshanan Raghunathan
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Publication number: 20160033879Abstract: Methods and controllers for controlling focus of ultraviolet light produced by a lithographic imaging system, and apparatuses for forming an integrated circuit employing the same are provided. In an embodiment, a method includes providing a wafer having a resist film disposed thereon. The resist film is patterned through illumination of a lithography mask with ultraviolet light at an off-normal incidence angle with a first test pattern formed at a first pitch and a second test pattern formed at a second pitch different from the first pitch. Non-telecentricity induced shift of the first and second test patterns is measured to produce relative shift data using a measurement device. Focus of the ultraviolet light is adjusted based upon comparison of the relative shift data to a pre-determined correlation between the non-telecentricity induced shift of the first and second test patterns as a function of focus error.Type: ApplicationFiled: July 30, 2014Publication date: February 4, 2016Inventors: Sudharshanan Raghunathan, Obert Reeves Wood II, Moshe E. Preil
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Patent number: 8956789Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes patterning a first photoresist layer overlying a mask blank that is mounted on a first chuck to form a first patterned photoresist layer. The mask blank is selectively etched using the first patterned photoresist layer to form a first patterned mask. The first patterned mask is mounted on a second chuck and a non-flatness compensation is determined. The first patterned mask is mounted on the first chuck and a second photoresist layer is patterned overlying the first patterned mask to form a second patterned photoresist layer. The second patterned photoresist layer includes a device pattern that has been adjusted using the non-flatness compensation. The first patterned mask is selectively etched using the second patterned photoresist layer to form a second patterned mask.Type: GrantFiled: March 15, 2013Date of Patent: February 17, 2015Assignee: GLOBALFOUNDRIES, Inc.Inventor: Sudharshanan Raghunathan
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Patent number: 8911920Abstract: A method for fabricating integrated circuits includes fabricating an EUV mask by providing a photomask having a border region. A photoresist is formed over the photomask and has a border region overlying the border region of the photomask. The method exposes an inner portion and an outer portion of the photoresist border region. The method removes the inner portion and the outer portion to expose the border region of the photomask. The border region of the photomask is etched using the photoresist as a mask to form the EUV mask with a non-reflective border. The photoresist is removed from the EUV mask. The method includes forming another photoresist over a partially-fabricated integrated circuit layer and patterning the photoresist by exposure to EUV light reflected from the EUV mask to expose portions of the partially-fabricated integrated circuit layer. Portions of the partially-fabricated integrated circuit layer and the photoresist are removed.Type: GrantFiled: March 15, 2013Date of Patent: December 16, 2014Assignee: GlobalFoundries, Inc.Inventors: Sudharshanan Raghunathan, Pawitter Mangat, Hui Peng Koh